Update ball_paddle.vhd, blocks.vhd, top.vhd files

ball_paddle.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09/21/2020 07:09:20 PM
+-- Design Name: 
+-- Module Name: ball_paddle - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity ball_paddle is
+	generic(
+		PADDLE_WIDTH : positive := 32;
+		SCREEN_WIDTH : positive := 512;
+		BALL_WIDTH : positive := 16;
+		BALL_START_X : positive := 17;
+		BALL_START_Y : positive := 239;
+		PADDLE_Y : positive := 216
+	);
+   	Port ( clk : in STD_LOGIC;
+	   reset : in STD_LOGIC;
+           button_r : in STD_LOGIC;
+	   button_l : in STD_LOGIC;
+           block_hit : in STD_LOGIC;
+	   paddle_hit_in : in STD_LOGIC;
+	   paddle_hit_out : out STD_LOGIC;
+	   ball_positionx_out : out STD_logic_vector(9 downto 0);
+	   ball_positiony_out : out STD_logic_vector(9 downto 0);
+	   ball_floor_hit : out std_logic;
+	   paddle_posx_out : out STD_LOGIC_VECTOR(9 downto 0)
+     
+);
+end ball_paddle;
+
+architecture Behavioral of ball_paddle is
+
+	signal ball_position_x, ball_next_position_x : unsigned(9 downto 0) := to_unsigned(BALL_START_X, 10);
+	signal ball_position_y, ball_next_position_y : unsigned(9 downto 0) := to_unsigned(BALL_START_Y, 10);
+	signal ball_direction_x, ball_next_direction_x : std_logic := '1';
+	signal ball_direction_y, ball_next_direction_y : std_logic := '0';
+	signal ball_floor_hit_s : STD_LOGIC;
+	signal padlle_posx_s, next_padlle_posx_s : unsigned(9 downto 0) :=to_unsigned(240, 10);
+
+begin
+
+process(clk)
+begin
+	if(clk' event and clk = '1') then
+		ball_position_x <= ball_next_position_x;
+		ball_position_y <= ball_next_position_y;
+		ball_direction_x <= ball_next_direction_x;
+		ball_direction_y <= ball_next_direction_y;
+		paddle_x_reg <= paddle_x_next;
+	end if;
+end process;
+
+NEXT_STATE: process(ball_position_x, ball_position_y, ball_direction_x, ball_direction_y, paddle_posx)
+begin
+	ball_next_position_x <= ball_position_x;
+	ball_next_position_y <= ball_position_y;
+	ball_next_direction_x <= ball_direction_x;
+	ball_next_direction_y <= ball_direction_y;
+
+	ball_next_position_x <= to_unsigned(BALL_START_X, 10) when ball_floor_hit_s = '1' or reset = '1' else
+			  ball_position_x + 1 when ball_direction_x = 1 else
+			  ball_position_x - 1 when ball_direction_x = 0;
+	ball_next_position_y <= to_unsigned(BALL_START_Y, 10) when ball_floor_hit_s = '1' or reset = '1' else
+			  ball_position_y + 1 when ball_direction_y = 1 else
+			  ball_position_y - 1 when ball_direction_y = 0;
+	ball_next_direction_x <= not ball_direction_x when (ball_position_x - BALL_WIDTH = 0) or (ball_position_x + BALL_WIDTH = 512);
+	ball_next_direction_y <= not ball_direction_y when (ball_position_y + BALL_WIDTH = 512) or (ball_paddle_hit = '1');
+	ball_floor_hit_s <= '1' when ball_position_y + BALL_WIDTH = 256 else
+		       '0';
+	ball_floor_hit <= ball_floor_hit_s;
+
+
+	next_padlle_posx_s <= paddle_posx;
+	
+	next_paddle_pos_x <= paddle_posx-1 when (button_l = '1') and (paddle_posx > 0) else
+			     paddle_posx+1 when (button_r = '1') and (paddle_posx + PADDLE_WIDTH < 512);
+
+	paddle_hit <= '1' when (ball_position_y + BALL_WIDTH = PADDLE_Y) and (ball_position_x > paddle_posx) and (ball_position_x < paddle_posx + PADDLE_WIDTH) else
+		      '0';
+end process;
+
+end Behavioral;

blocks.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 10/19/2020 04:27:55 PM
+-- Design Name: 
+-- Module Name: blocks - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity blocks is
+	generic(
+		BALL_WIDTH : positive := 16;
+	);
+    Port ( clk : in STD_LOGIC;
+	   ball_posx : in STD_LOGIC_VECTOR(9 downto 0);
+	   ball_posy : in STD_LOGIC_VECTOR(9 downto 0);
+	   reset : in STD_LOGIC;
+	   block_hit : STD_LOGIC
+     );
+end blocks;
+
+architecture Behavioral of blocks is
+
+	type ram_type is array(0 to 63) of STD_LOGIC_VECTOR(7 downto 0);
+	signal ram : ram_type := (
+		X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"00",X"00",X"00",X"00",X"00",X"00",
+		X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"00",X"00",X"00",X"00",X"00",X"00");
+begin
+
+PROCESS(clk)
+begin
+	
+	if (clk'event and clk = '1') then
+		
+	end if;
+end process;
+
+NEXT_STATE : process()
+
+begin
+	
+end process;
+
+end Behavioral;
\ No newline at end of file

top.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 09/21/2020 07:09:20 PM
+-- Design Name: 
+-- Module Name: top - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity top is
+	generic(
+		PADDLE_WIDTH : positive := 32;
+		SCREEN_WIDTH : positive := 512;
+		PADDLE_Y : positive := 216
+	);
+	Port ( clk : in STD_LOGIC;
+	   reset : in STD_LOGIC;
+           button_r : in STD_LOGIC;
+	   button_l : in STD_LOGIC;
+);
+end top;
+
+architecture Behavioral of top is
+
+	signal win, win_next, lose, lose_next : std_logic := '0';
+	signal block_hit : in STD_LOGIC;
+	signal paddle_hit_in : in STD_LOGIC;
+	signal paddle_hit_out : out STD_LOGIC;
+	signal ball_positionx_out : out STD_logic_vector(9 downto 0);
+	signal ball_posy : out STD_logic_vector(9 downto 0);
+	signal ball_posx : out std_logic;
+	signal paddle_posx_out : out STD_LOGIC_VECTOR(9 downto 0)
+
+begin
+
+process(clk)
+begin
+	if(clk' event and clk = '1') then
+		win <= win_next;
+		lose <= lose_next;
+	end if;
+end process;
+
+	ball_paddle0 : ball_paddle
+   	Port map( clk => clk,
+	   reset => reset,
+           button_r => button_r,
+	   button_l => button_l,
+           block_hit => block_hit,
+	   paddle_hit_in => paddle_hit_in,
+	   paddle_hit_out => paddle_hit_out,
+	   ball_positionx_out => ball_posx,
+	   ball_positiony_out => ball_posy,
+	   ball_floor_hit => ball_floor_hit,
+	   paddle_posx_out => paddle_posx_out
+     	);
+
+	blocks0 : blocks
+	Port ( clk => clk;
+	   ball_posx => ball_posx;
+	   ball_posy => ball_posy;
+	   reset => reset;
+	   block_hit => block_hit
+	);
+
+end Behavioral;