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blocks.vhd

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  • blocks.vhd 1.73 KiB
    ----------------------------------------------------------------------------------
    -- Company: 
    -- Engineer: 
    -- 
    -- Create Date: 10/19/2020 04:27:55 PM
    -- Design Name: 
    -- Module Name: blocks - Behavioral
    -- Project Name: 
    -- Target Devices: 
    -- Tool Versions: 
    -- Description: 
    -- 
    -- Dependencies: 
    -- 
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    -- 
    ----------------------------------------------------------------------------------
    
    
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.numeric_std.all;
    
    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
    --use IEEE.NUMERIC_STD.ALL;
    
    -- Uncomment the following library declaration if instantiating
    -- any Xilinx leaf cells in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;
    
    entity blocks is
    	generic(
    		BALL_WIDTH : positive := 16;
    	);
        Port ( clk : in STD_LOGIC;
    	   ball_posx : in STD_LOGIC_VECTOR(9 downto 0);
    	   ball_posy : in STD_LOGIC_VECTOR(9 downto 0);
    	   reset : in STD_LOGIC;
    	   block_hit : STD_LOGIC
         );
    end blocks;
    
    architecture Behavioral of blocks is
    
    	type ram_type is array(0 to 63) of STD_LOGIC_VECTOR(7 downto 0);
    	signal ram : ram_type := (
    		X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"00",X"00",X"00",X"00",X"00",X"00",
    		X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"00",X"00",X"00",X"00",X"00",X"00",
    		X"FC",X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"00",X"00",X"00",X"00",X"00",X"00",
    		X"03",X"1F",X"FC",X"03",X"1C",X"FC",X"03",X"1F",X"FC",X"03",X"00",X"00",X"00",X"00",X"00",X"00");
    begin
    
    PROCESS(clk)
    begin
    	
    	if (clk'event and clk = '1') then
    		
    	end if;
    end process;
    
    NEXT_STATE : process()
    
    begin
    	
    end process;
    
    end Behavioral;