top.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2020 07:09:20 PM
-- Design Name: 
-- Module Name: top - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
	generic(
		PADDLE_WIDTH : positive := 32;
		SCREEN_WIDTH : positive := 512;
		PADDLE_Y : positive := 216
	);
	Port ( clk : in STD_LOGIC;
	   reset : in STD_LOGIC;
           button_r : in STD_LOGIC;
	   button_l : in STD_LOGIC;
);
end top;

architecture Behavioral of top is

	signal win, win_next, lose, lose_next : std_logic := '0';
	signal block_hit : in STD_LOGIC;
	signal paddle_hit_in : in STD_LOGIC;
	signal paddle_hit_out : out STD_LOGIC;
	signal ball_positionx_out : out STD_logic_vector(9 downto 0);
	signal ball_posy : out STD_logic_vector(9 downto 0);
	signal ball_posx : out std_logic;
	signal paddle_posx_out : out STD_LOGIC_VECTOR(9 downto 0)

begin

process(clk)
begin
	if(clk' event and clk = '1') then
		win <= win_next;
		lose <= lose_next;
	end if;
end process;

	ball_paddle0 : ball_paddle
   	Port map( clk => clk,
	   reset => reset,
           button_r => button_r,
	   button_l => button_l,
           block_hit => block_hit,
	   paddle_hit_in => paddle_hit_in,
	   paddle_hit_out => paddle_hit_out,
	   ball_positionx_out => ball_posx,
	   ball_positiony_out => ball_posy,
	   ball_floor_hit => ball_floor_hit,
	   paddle_posx_out => paddle_posx_out
     	);

	blocks0 : blocks
	Port ( clk => clk;
	   ball_posx => ball_posx;
	   ball_posy => ball_posy;
	   reset => reset;
	   block_hit => block_hit
	);

end Behavioral;