ball_paddle.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09/21/2020 07:09:20 PM
-- Design Name: 
-- Module Name: ball_paddle - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ball_paddle is
	generic(
		PADDLE_WIDTH : positive := 32;
		SCREEN_WIDTH : positive := 512;
		BALL_WIDTH : positive := 16;
		BALL_START_X : positive := 17;
		BALL_START_Y : positive := 239;
		PADDLE_Y : positive := 216
	);
   	Port ( clk : in STD_LOGIC;
	   reset : in STD_LOGIC;
           button_r : in STD_LOGIC;
	   button_l : in STD_LOGIC;
           block_hit : in STD_LOGIC;
	   paddle_hit_in : in STD_LOGIC;
	   paddle_hit_out : out STD_LOGIC;
	   ball_positionx_out : out STD_logic_vector(9 downto 0);
	   ball_positiony_out : out STD_logic_vector(9 downto 0);
	   ball_floor_hit : out std_logic;
	   paddle_posx_out : out STD_LOGIC_VECTOR(9 downto 0)
     
);
end ball_paddle;

architecture Behavioral of ball_paddle is

	signal ball_position_x, ball_next_position_x : unsigned(9 downto 0) := to_unsigned(BALL_START_X, 10);
	signal ball_position_y, ball_next_position_y : unsigned(9 downto 0) := to_unsigned(BALL_START_Y, 10);
	signal ball_direction_x, ball_next_direction_x : std_logic := '1';
	signal ball_direction_y, ball_next_direction_y : std_logic := '0';
	signal ball_floor_hit_s : STD_LOGIC;
	signal padlle_posx_s, next_padlle_posx_s : unsigned(9 downto 0) :=to_unsigned(240, 10);

begin

process(clk)
begin