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fpga_project
Commits
d2e363d2
Commit
d2e363d2
authored
6 years ago
by
vagle
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added one hertz clock
clock for cells
parent
436e9f22
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game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd
+61
-0
61 additions, 0 deletions
...life/game_of_life.srcs/sources_1/new/one_second_clock.vhd
game_of_life/game_of_life.xpr
+7
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7 additions, 0 deletions
game_of_life/game_of_life.xpr
with
68 additions
and
0 deletions
game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd
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d2e363d2
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/26/2018 02:20:05 PM
-- Design Name:
-- Module Name: one_second_clock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use
IEEE
.
NUMERIC_STD
.
ALL
;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity
one_second_clock
is
Port
(
clock_in
:
in
STD_LOGIC
;
locked
:
in
STD_LOGIC
;
clock_out
:
out
STD_LOGIC
);
end
one_second_clock
;
architecture
Behavioral
of
one_second_clock
is
signal
counter
:
unsigned
(
13
downto
0
);
signal
clock_out_sig
:
std_logic
:
=
'0'
;
begin
clk_gen
:
process
(
clock_in
)
begin
if
clock_in
'event
and
clock_in
=
'1'
and
locked
=
'1'
then
if
counter
=
12499
then
counter
<=
(
others
=>
'0'
);
clock_out_sig
<=
not
clock_out_sig
;
else
counter
<=
counter
+
1
;
end
if
;
end
if
;
end
process
;
clock_out
<=
clock_out_sig
;
end
Behavioral
;
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game_of_life/game_of_life.xpr
+
7
−
0
View file @
d2e363d2
...
...
@@ -63,6 +63,13 @@
<Attr
Name=
"UsedIn"
Val=
"simulation"
/>
</FileInfo>
</File>
<File
Path=
"$PSRCDIR/sources_1/new/one_second_clock.vhd"
>
<FileInfo>
<Attr
Name=
"AutoDisabled"
Val=
"1"
/>
<Attr
Name=
"UsedIn"
Val=
"synthesis"
/>
<Attr
Name=
"UsedIn"
Val=
"simulation"
/>
</FileInfo>
</File>
<Config>
<Option
Name=
"DesignMode"
Val=
"RTL"
/>
<Option
Name=
"TopModule"
Val=
"game_of_life"
/>
...
...
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