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Commit 436e9f22 authored by vagle's avatar vagle
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inserted clock

parent 73b80e7e
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...@@ -32,12 +32,41 @@ use IEEE.STD_LOGIC_1164.ALL; ...@@ -32,12 +32,41 @@ use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all; --use UNISIM.VComponents.all;
entity game_of_life is entity game_of_life is
-- Port ( ); Port (
clk_sys : in STD_LOGIC
);
end game_of_life; end game_of_life;
architecture Behavioral of game_of_life is architecture Behavioral of game_of_life is
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_25MHz_out : out std_logic;
-- Status and control signals
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal locked, inner_clk : STD_LOGIC;
begin begin
tic_toc : clk_wiz_0
port map (
-- Clock out ports
clk_25MHz_out => inner_clk,
-- Status and control signals
locked => locked,
-- Clock in ports
clk_in1 => clk_sys
);
synchron : process(inner_clk)
begin
--
end process;
end Behavioral; end Behavioral;
...@@ -40,13 +40,13 @@ ...@@ -40,13 +40,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/> <Option Name="WTXSimExportSim" Val="1"/>
<Option Name="WTModelSimExportSim" Val="0"/> <Option Name="WTModelSimExportSim" Val="1"/>
<Option Name="WTQuestaExportSim" Val="0"/> <Option Name="WTQuestaExportSim" Val="1"/>
<Option Name="WTIesExportSim" Val="0"/> <Option Name="WTIesExportSim" Val="1"/>
<Option Name="WTVcsExportSim" Val="0"/> <Option Name="WTVcsExportSim" Val="1"/>
<Option Name="WTRivieraExportSim" Val="0"/> <Option Name="WTRivieraExportSim" Val="1"/>
<Option Name="WTActivehdlExportSim" Val="0"/> <Option Name="WTActivehdlExportSim" Val="1"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
...@@ -92,6 +92,19 @@ ...@@ -92,6 +92,19 @@
<Option Name="SrcSet" Val="sources_1"/> <Option Name="SrcSet" Val="sources_1"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="clk_wiz_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
<File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clk_wiz_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets> </FileSets>
<Simulators> <Simulators>
<Simulator Name="XSim"> <Simulator Name="XSim">
...@@ -125,6 +138,17 @@ ...@@ -125,6 +138,17 @@
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7z020clg484-1" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
...@@ -143,6 +167,24 @@ ...@@ -143,6 +167,24 @@
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/> <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run> </Run>
<Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs> </Runs>
<Board> <Board>
<Jumpers/> <Jumpers/>
......
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