From d2e363d2c29991c01ab043944a3c548075ac9ae6 Mon Sep 17 00:00:00 2001 From: vagle <vagilevente@gmail.com> Date: Mon, 26 Nov 2018 14:28:56 +0100 Subject: [PATCH] added one hertz clock clock for cells --- .../sources_1/new/one_second_clock.vhd | 61 +++++++++++++++++++ game_of_life/game_of_life.xpr | 7 +++ 2 files changed, 68 insertions(+) create mode 100644 game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd diff --git a/game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd b/game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd new file mode 100644 index 0000000..211ec8e --- /dev/null +++ b/game_of_life/game_of_life.srcs/sources_1/new/one_second_clock.vhd @@ -0,0 +1,61 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11/26/2018 02:20:05 PM +-- Design Name: +-- Module Name: one_second_clock - Behavioral +-- Project Name: +-- Target Devices: +-- Tool Versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx leaf cells in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity one_second_clock is + Port ( clock_in : in STD_LOGIC; + locked : in STD_LOGIC; + clock_out : out STD_LOGIC); +end one_second_clock; + +architecture Behavioral of one_second_clock is + +signal counter : unsigned(13 downto 0); +signal clock_out_sig : std_logic := '0'; + +begin + +clk_gen : process(clock_in) +begin + if clock_in'event and clock_in = '1' and locked = '1' then + if counter = 12499 then + counter <= (others => '0'); + clock_out_sig <= not clock_out_sig; + else + counter <= counter + 1; + end if; + end if; +end process; + +clock_out <= clock_out_sig; + +end Behavioral; diff --git a/game_of_life/game_of_life.xpr b/game_of_life/game_of_life.xpr index fe8ac3f..4d3fef0 100644 --- a/game_of_life/game_of_life.xpr +++ b/game_of_life/game_of_life.xpr @@ -63,6 +63,13 @@ <Attr Name="UsedIn" Val="simulation"/> </FileInfo> </File> + <File Path="$PSRCDIR/sources_1/new/one_second_clock.vhd"> + <FileInfo> + <Attr Name="AutoDisabled" Val="1"/> + <Attr Name="UsedIn" Val="synthesis"/> + <Attr Name="UsedIn" Val="simulation"/> + </FileInfo> + </File> <Config> <Option Name="DesignMode" Val="RTL"/> <Option Name="TopModule" Val="game_of_life"/> -- GitLab