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Commit f10905b5 authored by vagle's avatar vagle
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Merge branch 'master' of dev.itk.ppke.hu:mlinko.peter/fpga_project

parents 33ff0994 7c3aa327
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game_of_life/game_of_life.cache/wt/gui_handlers.wdf
+ 17
− 6
View file @ f10905b5
version:1 version:1
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eof:2151772892
game_of_life/game_of_life.cache/wt/java_command_handlers.wdf
+ 5
− 1
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version:1 version:1
70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:31:00:00
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eof:1203675202 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7361766566696c6570726f787968616e646c6572:31:00:00
eof:2487913160
game_of_life/game_of_life.cache/wt/webtalk_pa.xml
+ 23
− 8
View file @ f10905b5
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Mon Nov 26 13:12:34 2018"> <application name="pa" timeStamp="Tue Nov 27 16:00:41 2018">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="01722960b9c445a0b34a6663716d359c" type="ProjectID"/> <property name="ProjectID" value="01722960b9c445a0b34a6663716d359c" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/> <property name="ProjectIteration" value="1" type="ProjectIteration"/>
...@@ -17,30 +17,45 @@ This means code written to parse this file will need to be revisited each subseq ...@@ -17,30 +17,45 @@ This means code written to parse this file will need to be revisited each subseq
<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/> <property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
</item> </item>
<item name="Java Command Handlers"> <item name="Java Command Handlers">
<property name="AddSources" value="1" type="JavaHandler"/>
<property name="CoreView" value="1" type="JavaHandler"/> <property name="CoreView" value="1" type="JavaHandler"/>
<property name="CustomizeCore" value="1" type="JavaHandler"/> <property name="CustomizeCore" value="1" type="JavaHandler"/>
<property name="EditDelete" value="1" type="JavaHandler"/>
<property name="EditUndo" value="1" type="JavaHandler"/>
<property name="NewProject" value="2" type="JavaHandler"/> <property name="NewProject" value="2" type="JavaHandler"/>
<property name="SaveFileProxyHandler" value="1" type="JavaHandler"/>
</item> </item>
<item name="Gui Handlers"> <item name="Gui Handlers">
<property name="BaseDialog_OK" value="4" type="GuiHandlerData"/> <property name="AbstractCombinedPanel_ADD_ELEMENT" value="3" type="GuiHandlerData"/>
<property name="BaseDialog_CANCEL" value="1" type="GuiHandlerData"/>
<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>
<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/> <property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/> <property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="3" type="GuiHandlerData"/>
<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/> <property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/> <property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/> <property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="18" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="2" type="GuiHandlerData"/> <property name="FileSetPanel_FILE_SET_PANEL_TREE" value="24" type="GuiHandlerData"/>
<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="3" type="GuiHandlerData"/>
<property name="GettingStartedView_CREATE_NEW_PROJECT" value="2" type="GuiHandlerData"/> <property name="GettingStartedView_CREATE_NEW_PROJECT" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_EXPORT" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_FILE" value="1" type="GuiHandlerData"/>
<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
<property name="PACommandNames_ADD_SOURCES" value="1" type="GuiHandlerData"/>
<property name="PartChooser_BOARDS" value="2" type="GuiHandlerData"/> <property name="PartChooser_BOARDS" value="2" type="GuiHandlerData"/>
<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/> <property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/> <property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
<property name="RDICommands_DELETE" value="1" type="GuiHandlerData"/>
<property name="RemoveSourcesDialog_ALSO_DELETE" value="1" type="GuiHandlerData"/>
<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/> <property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/> <property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/> <property name="SrcChooserPanel_CREATE_FILE" value="3" type="GuiHandlerData"/>
<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
</item> </item>
<item name="Other"> <item name="Other">
<property name="GuiMode" value="10" type="GuiMode"/> <property name="GuiMode" value="4" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/> <property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="8" type="TclMode"/> <property name="TclMode" value="2" type="TclMode"/>
</item> </item>
</section> </section>
</application> </application>
......
game_of_life/game_of_life.srcs/sources_1/new/cell.vhd 0 → 100644
+ 95
− 0
View file @ f10905b5
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/26/2018 01:05:37 PM
-- Design Name:
-- Module Name: game_of_life - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cell is
Port (
clk_1hz : in STD_LOGIC; -- this signal shows when to refresh
locked : in STD_LOGIC; -- locked shows if the gol's inner clock is locked
switch : in STD_LOGIC; -- switch between user input and automatic working
flip_val : inout STD_LOGIC; -- signal to switch state if user input is activated (switch=true)
neighbours : in STD_LOGIC_VECTOR(1 to 8);-- state of neighbours
output : out STD_LOGIC -- output of the cell
);
end cell;
architecture Behavioral of cell is
signal state, next_state : STD_LOGIC := '0';
signal neighbour_count : UNSIGNED(3 downto 0);
signal flip_val_sig : STD_LOGIC;
begin
life_cycle : process(clk_1hz) -- for now we dont care about the switches, later should written
begin
if clk_1hz'event and clk_1hz='1' and locked='1' and switch='1' then
if neighbour_count=3 then
next_state <= '1';
elsif neighbour_count=2 then
next_state <= state;
elsif neighbour_count<2 or neighbour_count>3 then
next_state <= '0';
end if;
state <= next_state;
elsif clk_1hz'event and clk_1hz='1' and locked='1' and switch='0' then
if flip_val_sig='1' then
next_state <= not state;
end if;
state <= next_state;
end if;
end process; -- life_cycle
count_neighbours : process (clk_1hz) -- this process calculates active neighbours, if the clk chages to 0
variable temp_count : UNSIGNED(3 downto 0);
begin
if clk_1hz'event and clk_1hz='0' and locked='1' and switch='1' then
temp_count := (others=>'0');
for n in neighbours'range loop
if neighbours(n) = '1' then
temp_count := temp_count+1;
end if;
end loop;
neighbour_count <= temp_count;
end if;
end process; -- count_neighbours
handle_flip_val_input : process (flip_val)
begin
if flip_val'event and flip_val='0' then
flip_val_sig<='1';
flip_val<='0';
end if;
end process;
end Behavioral;
\ No newline at end of file
game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
+ 35
− 1
View file @ f10905b5
...@@ -50,7 +50,33 @@ port ...@@ -50,7 +50,33 @@ port
); );
end component; end component;
signal locked, inner_clk : STD_LOGIC; component one_second_clock
port
(
clock_in : in STD_LOGIC;
locked : in STD_LOGIC;
clock_out : out STD_LOGIC
);
end component;
component cell
port
(
clk_1hz : in STD_LOGIC;
locked : in STD_LOGIC;
switch : in STD_LOGIC;
flip_val : inout STD_LOGIC;
neighbours : in STD_LOGIC_VECTOR(1 to 8);
output : out STD_LOGIC
);
end component;
signal locked, inner_clk, one_sec_clk : STD_LOGIC;
-- the cell_outputs signal holds the output of the cells
-- the 0th element holds the boundary condition
-- we have 64×48 cells
signal cell_outputs : STD_LOGIC_VECTOR(0 to 3072);
begin begin
...@@ -64,6 +90,14 @@ tic_toc : clk_wiz_0 ...@@ -64,6 +90,14 @@ tic_toc : clk_wiz_0
clk_in1 => clk_sys clk_in1 => clk_sys
); );
one_hertz_gen : one_second_clock
port map
(
clock_in => inner_clk,
locked => locked,
clock_out => one_sec_clk
);
synchron : process(inner_clk) synchron : process(inner_clk)
begin begin
-- --
......
game_of_life/game_of_life.xpr
+ 8
− 2
View file @ f10905b5
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
<!-- --> <!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --> <!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/home/vagle/fpga_project/game_of_life/game_of_life.xpr"> <Project Version="7" Minor="35" Path="/home/link/Documents/ppke/fpga/fpga_project/game_of_life/game_of_life.xpr">
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="371a98f33a2a4b6a881ffa6392349aed"/> <Option Name="Id" Val="371a98f33a2a4b6a881ffa6392349aed"/>
...@@ -57,13 +57,19 @@ ...@@ -57,13 +57,19 @@
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/one_second_clock.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PSRCDIR/sources_1/new/game_of_life.vhd"> <File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PSRCDIR/sources_1/new/one_second_clock.vhd"> <File Path="$PSRCDIR/sources_1/new/cell.vhd">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/> <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
......
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