Skip to content
Snippets Groups Projects
Commit 06e01d3d authored by Mlinkó Péter's avatar Mlinkó Péter
Browse files

V2 project with some files

parent baa9dfb0
Branches
No related tags found
No related merge requests found
Show whitespace changes
Inline Side-by-side
game_of_life_v2/game_of_life_v2.cache/wt/project.wpc 0 → 100644
+ 3
− 0
View file @ 06e01d3d
version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
eof:
game_of_life_v2/game_of_life_v2.hw/game_of_life_v2.lpr 0 → 100644
+ 6
− 0
View file @ 06e01d3d
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<labtools version="1" minor="0"/>
game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc 0 → 100644
+ 29
− 0
View file @ 06e01d3d
set_property PACKAGE_PIN Y9 [get_ports {GCLK}]; # "GCLK"
set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}]; # "VGA-B1"
set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}]; # "VGA-B2"
set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}]; # "VGA-B3"
set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}]; # "VGA-B4"
set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}]; # "VGA-G1"
set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}]; # "VGA-G2"
set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}]; # "VGA-G3"
set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}]; # "VGA-G4"
set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}]; # "VGA-HS"
set_property PACKAGE_PIN V20 [get_ports {VGA_R1}]; # "VGA-R1"
set_property PACKAGE_PIN U20 [get_ports {VGA_R2}]; # "VGA-R2"
set_property PACKAGE_PIN V19 [get_ports {VGA_R3}]; # "VGA-R3"
set_property PACKAGE_PIN V18 [get_ports {VGA_R4}]; # "VGA-R4"
set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}]; # "VGA-VS"
set_property PACKAGE_PIN P16 [get_ports {BTNC}]; # "BTNC"
set_property PACKAGE_PIN R16 [get_ports {BTND}]; # "BTND"
set_property PACKAGE_PIN N15 [get_ports {BTNL}]; # "BTNL"
set_property PACKAGE_PIN R18 [get_ports {BTNR}]; # "BTNR"
set_property PACKAGE_PIN T18 [get_ports {BTNU}]; # "BTNU"
set_property PACKAGE_PIN F22 [get_ports {SW0}]; # "SW0"
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd 0 → 100644
+ 178
− 0
View file @ 06e01d3d
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12/10/2018 01:49:49 PM
-- Design Name:
-- Module Name: game_of_life - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity game_of_life is
generic (cell_number : positive := 32);
Port ( clk : in STD_LOGIC;
switch_mode : in STD_LOGIC; -- 0: editor, 1: simulation
--cursor_position_x : in UNSIGNED(9 downto 0); -- cursor's position in the horizontal axis
--cursor_position_y : in UNSIGNED(9 downto 0); -- cursor's position in the vertical axis
Hsync : out STD_LOGIC; -- horizontal synchronization controll sign
Vsync : out STD_LOGIC; -- vertical synchronization controll sign
frame : out STD_LOGIC_VECTOR(11 downto 0) -- RGB code of actual pixel point
);
end game_of_life;
architecture Behavioral of game_of_life is
component clk_wiz_0
port
(-- Clock in ports
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
locked : out std_logic;
clk_in1 : in std_logic
);
end component;
signal clk_25MHz, locked : std_logic;
signal cells : std_logic_vector(0 to cell_number-1) := (others => '0');
signal cells_to_draw : std_logic_vector(0 to cell_number-1) := (others => '0');
-- drawing period's constants
constant HORIZONTAL_SYNC_PULSE : integer := 800;
constant VERTICAL_SYNC_PULSE : integer := 521;
constant HORIZONTAL_DISPLAY_TIME : integer := 640;
constant VERTICAL_DISPLAY_TIME : integer := 480;
constant HORIZONTAL_PULSE_WIDTH : integer := 96;
constant VERTICAL_PULSE_WIDTH : integer := 2;
constant HORIZONTAL_FRONT_PORCH : integer := 16;
constant VERTICAL_FRONT_PORCH : integer := 10;
constant HORIZONTAL_BACK_PORCH : integer := 48;
constant VERTICAL_BACK_PORCH : integer := 29;
-- helpers for drawing
signal horizontal_counter, vertical_counter : unsigned(9 downto 0);
signal Hsync_sig, Vsync_sig : std_logic;
signal frame_sig : std_logic_vector(11 downto 0);
-- simulation processers
signal shift_register_top : std_logic_vector(0 to cell_number-1);
signal shift_register_middle : std_logic_vector(0 to cell_number-1);
signal neighbours : std_logic_vector(0 to 8);
begin
clk_gen_25MHz : clk_wiz_0
port map (
-- Clock out ports
clk_out1 => clk_25MHz,
-- Status and control signals
locked => locked,
-- Clock in ports
clk_in1 => clk
);
options : process(clk_25MHz,locked)
begin
if locked = '0' then
horizontal_counter <= (others => '0');
vertical_counter <= (others => '0');
Hsync_sig <= '1';
Vsync_sig <= '1';
shift_register_top <= (others => '0');
shift_register_middle <= (others => '0');
neighbours <= (others => '0');
else
if clk_25MHz'event and clk_25MHz = '1' then
-- output change
if horizontal_counter(9 downto 3) < cell_number and vertical_counter(9 downto 3) < cell_number then
-- editor mode
if switch_mode = '0' then
--if cursor_position_x <= horizontal_counter and cursor_position_x+8 > horizontal_counter and cursor_position_y <= vertical_counter and cursor_position_y+8 > vertical_counter then
-- if cells_to_draw(to_integer(vertical_counter(9 downto 3) * to_unsigned(cell_number,8) + horizontal_counter(9 downto 3))) = '0' then
-- frame_sig <= "000011110000";
-- else
-- frame_sig <= "111100000000";
-- end if;
--else
frame_sig <= (others => cells_to_draw(to_integer(vertical_counter(9 downto 3) * to_unsigned(cell_number,8) + horizontal_counter(9 downto 3))));
--end if;
-- simulation mode
else
frame_sig <= (others => cells_to_draw(to_integer(vertical_counter(9 downto 3) * to_unsigned(cell_number,8) + horizontal_counter(9 downto 3))));
end if;
else
frame_sig <= (others => '0');
end if;
-- handle shift registers
if horizontal_counter(9 downto 3) < cell_number and vertical_counter(9 downto 3) < cell_number then
shift_register_top <= shift_register_top(1 to cell_number-1) & shift_register_middle(0);
shift_register_middle <= shift_register_middle(1 to cell_number-1) & cells(to_integer(vertical_counter(9 downto 3) * to_unsigned(cell_number,8) + horizontal_counter(9 downto 3)));
neighbours <= neighbours(3 to 8) & shift_register_top(0) & shift_register_middle(0) & cells(to_integer(vertical_counter(9 downto 3) * to_unsigned(cell_number,8) + horizontal_counter(9 downto 3)));
-- TODO
end if;
-- sign options
if horizontal_counter = HORIZONTAL_DISPLAY_TIME + HORIZONTAL_FRONT_PORCH - 1 then
Hsync_sig <= '0';
end if;
if horizontal_counter = HORIZONTAL_DISPLAY_TIME + HORIZONTAL_FRONT_PORCH + HORIZONTAL_PULSE_WIDTH - 1 then
Hsync_sig <= '1';
end if;
if vertical_counter = VERTICAL_DISPLAY_TIME + VERTICAL_FRONT_PORCH - 1 then
Vsync_sig <= '0';
end if;
if vertical_counter = VERTICAL_DISPLAY_TIME + VERTICAL_FRONT_PORCH + VERTICAL_PULSE_WIDTH - 1 then
Vsync_sig <= '1';
end if;
-- position changing
if vertical_counter = VERTICAL_SYNC_PULSE-1 then
vertical_counter <= (others => '0');
end if;
if horizontal_counter = HORIZONTAL_SYNC_PULSE-1 then
horizontal_counter <= (others => '0');
vertical_counter <= vertical_counter + 1;
else
horizontal_counter <= horizontal_counter + 1;
end if;
end if;
end if;
end process;
draw : process(clk_25MHz)
begin
if clk_25MHz'event and clk_25MHz = '1' then
Hsync <= Hsync_sig;
Vsync <= Vsync_sig;
frame <= frame_sig;
end if;
end process;
end Behavioral;
game_of_life_v2/game_of_life_v2.xpr 0 → 100644
+ 150
− 0
View file @ 06e01d3d
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2017.4 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="35" Path="/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="3e265ee7ec4345a3a8b6f0b7f2e11715"/>
<Option Name="Part" Val="xc7z020clg484-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="em.avnet.com:zed:part0:1.3"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSAVendor" Val="xilinx"/>
<Option Name="DSABoardId" Val="zed"/>
<Option Name="DSANumComputeUnits" Val="60"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="0"/>
<Option Name="WTModelSimExportSim" Val="0"/>
<Option Name="WTQuestaExportSim" Val="0"/>
<Option Name="WTIesExportSim" Val="0"/>
<Option Name="WTVcsExportSim" Val="0"/>
<Option Name="WTRivieraExportSim" Val="0"/>
<Option Name="WTActivehdlExportSim" Val="0"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="SimTypes" Val="rtl"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="game_of_life"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PSRCDIR/constrs_1/new/constraints.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="game_of_life"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="IES">
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
</Simulator>
<Simulator Name="VCS">
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
<Board>
<Jumpers/>
</Board>
</Project>
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment