comments + xdc

game_of_life/game_of_life.srcs/constrs_1/new/game_of_life.xdc

+set_property PACKAGE_PIN Y9 [get_ports {GCLK}];  # "GCLK"
+
+set_property PACKAGE_PIN Y21  [get_ports {VGA_B1}];  # "VGA-B1"
+set_property PACKAGE_PIN Y20  [get_ports {VGA_B2}];  # "VGA-B2"
+set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}];  # "VGA-B3"
+set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}];  # "VGA-B4"
+set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}];  # "VGA-G1"
+set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}];  # "VGA-G2"
+set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}];  # "VGA-G3"
+set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}];  # "VGA-G4"
+set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}];  # "VGA-HS"
+set_property PACKAGE_PIN V20  [get_ports {VGA_R1}];  # "VGA-R1"
+set_property PACKAGE_PIN U20  [get_ports {VGA_R2}];  # "VGA-R2"
+set_property PACKAGE_PIN V19  [get_ports {VGA_R3}];  # "VGA-R3"
+set_property PACKAGE_PIN V18  [get_ports {VGA_R4}];  # "VGA-R4"
+set_property PACKAGE_PIN Y19  [get_ports {VGA_VS}];  # "VGA-VS"
+
+set_property PACKAGE_PIN P16 [get_ports {BTNC}];  # "BTNC"
+set_property PACKAGE_PIN R16 [get_ports {BTND}];  # "BTND"
+set_property PACKAGE_PIN N15 [get_ports {BTNL}];  # "BTNL"
+set_property PACKAGE_PIN R18 [get_ports {BTNR}];  # "BTNR"
+set_property PACKAGE_PIN T18 [get_ports {BTNU}];  # "BTNU"
+
+set_property PACKAGE_PIN F22 [get_ports {SW0}];  # "SW0"
+
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];

game_of_life/game_of_life.srcs/sources_1/new/editor.vhd

@@ -32,17 +32,17 @@ use IEEE.NUMERIC_STD.ALL;
 --use UNISIM.VComponents.all;
 
 entity editor is
-    Port ( clk : in STD_LOGIC;
-           locked : in STD_LOGIC;
-           move_left : in STD_LOGIC;
-           move_right : in STD_LOGIC;
-           move_up : in STD_LOGIC;
-           move_down : in STD_LOGIC;
-           set_cell : in STD_LOGIC;
-           
-           cursor_position_x : out UNSIGNED(9 downto 0);
-           cursor_position_y : out UNSIGNED(9 downto 0);
-           invert : out STD_LOGIC);
+    Port ( clk : in STD_LOGIC;                            --
+           locked : in STD_LOGIC;                         --
+           move_left : in STD_LOGIC;                      --
+           move_right : in STD_LOGIC;                     --
+           move_up : in STD_LOGIC;                        --
+           move_down : in STD_LOGIC;                      --
+           set_cell : in STD_LOGIC;                       --
+           
+           cursor_position_x : out UNSIGNED(9 downto 0);  --
+           cursor_position_y : out UNSIGNED(9 downto 0);  --
+           invert : out STD_LOGIC);                       --
 end editor;
 
 architecture Behavioral of editor is
@@ -72,7 +72,7 @@ begin
         prev_set_cell <= set_cell;
     else
         if clk'event and clk = '1' then
-            -- moving
+            -- moving with cursor
             if prev_move_left = '0' and move_left = '1' and cursor_pos_x /= 0 then
                 cursor_pos_x <= cursor_pos_x - 8;
                 cursor_position_x <= cursor_pos_x - 8;
@@ -90,7 +90,7 @@ begin
                 cursor_position_y <= cursor_pos_y + 8;
             end if;
             
-            -- set letter
+            -- set cell's value
             if prev_set_cell = '0' and set_cell = '1' then
                 invert <= '1';
             else

game_of_life/game_of_life.srcs/sources_1/new/vga_drawer.vhd

@@ -32,20 +32,21 @@ use IEEE.NUMERIC_STD.ALL;
 --use UNISIM.VComponents.all;
 
 entity vga_drawer is
-    Port ( clk_25MHz : in STD_LOGIC;                    -- input clock signal with 25 MHz
-           locked : in STD_LOGIC;                       --
+    Port ( clk_25MHz : in STD_LOGIC;                    -- synchron clock signal with 25 MHz
+           locked : in STD_LOGIC;                       -- clk sign is not stable
            cells : in STD_LOGIC_VECTOR(0 to 4799);      -- 
            switch_mode : in STD_LOGIC;                  -- 0: editor, 1: simulation
-           cursor_position_x : in UNSIGNED(9 downto 0); --
-           cursor_position_y : in UNSIGNED(9 downto 0); --
+           cursor_position_x : in UNSIGNED(9 downto 0); -- cursor's position in the horizontal axis
+           cursor_position_y : in UNSIGNED(9 downto 0); -- cursor's position in the vertical axis
            
-           Hsync : out STD_LOGIC;                       --
-           Vsync : out STD_LOGIC;                       --
-           frame : out STD_LOGIC_VECTOR(11 downto 0));  --
+           Hsync : out STD_LOGIC;                       -- horizontal synchronization controll sign
+           Vsync : out STD_LOGIC;                       -- vertical synchronization controll sign
+           frame : out STD_LOGIC_VECTOR(11 downto 0));  -- RGB code of actual pixel point
 end vga_drawer;
 
 architecture Behavioral of vga_drawer is
 
+-- drawing period's constants
 constant HORIZONTAL_SYNC_PULSE : integer := 800;
 constant VERTICAL_SYNC_PULSE : integer := 521;
 constant HORIZONTAL_DISPLAY_TIME : integer := 640;
@@ -57,6 +58,7 @@ constant VERTICAL_FRONT_PORCH : integer := 10;
 constant HORIZONTAL_BACK_PORCH : integer := 48;
 constant VERTICAL_BACK_PORCH : integer := 29;
 
+-- helpers for drawing
 signal horizontal_counter, vertical_counter : unsigned(9 downto 0);
 signal Hsync_sig, Vsync_sig : std_logic;
 signal frame_sig : std_logic_vector(11 downto 0);