This is a commit

game_of_life/game_of_life.cache/wt/project.wpc

 version:1
-6d6f64655f636f756e7465727c4755494d6f6465:3
+6d6f64655f636f756e7465727c4755494d6f6465:4
 eof:

game_of_life/game_of_life.srcs/sources_1/new/cell.vhd

@@ -36,7 +36,7 @@ entity cell is
         clk_1hz : in STD_LOGIC;                  -- this signal shows when to refresh
         locked : in STD_LOGIC;                   -- locked shows if the gol's inner clock is locked
         switch : in STD_LOGIC;                   -- switch between user input and automatic working
-        flip_val : inout STD_LOGIC;              -- signal to switch state if user input is activated (switch=true)
+        flip_val : in STD_LOGIC;                 -- signal to switch state if user input is activated (switch=true)
         neighbours : in STD_LOGIC_VECTOR(1 to 8);-- state of neighbours
         output : out STD_LOGIC                   -- output of the cell
     );
@@ -57,7 +57,7 @@ begin
                 next_state <= '1';
             elsif neighbour_count=2 then
                 next_state <= state;
-            elsif neighbour_count<2 or neighbour_count>3 then
+            else
                 next_state <= '0';
             end if;
             state <= next_state;
@@ -86,9 +86,8 @@ begin
  
     handle_flip_val_input : process (flip_val)
     begin
-        if flip_val'event and flip_val='0' then
-            flip_val_sig<='1';
-            flip_val<='0';
+        if flip_val'event and flip_val='1' then
+            next_state <= not state;
         end if;
     end process;
  

game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd

@@ -76,10 +76,25 @@ signal locked, inner_clk, one_sec_clk : STD_LOGIC;
 -- the cell_outputs signal holds the output of the cells
 -- the 0th element holds the boundary condition
 -- we have 64×48 cells
-signal cell_outputs : STD_LOGIC_VECTOR(0 to 3072);
+signal cell_outputs : STD_LOGIC_VECTOR(0 to 4799);
+signal cell_flipvals : STD_LOGIC_VECTOR(0 to 4799);
+constant bound_cond : STD_LOGIC := '0';
 
 begin
 
+table_of_cells: for i in 0 to 60 generate
+begin
+    row_of_cells: for j in 0 to 80 generate
+    begin
+    
+        if i=0 and j=0 then
+            cell:
+        
+        endif;
+    
+    end generate;
+end generate;
+
 tic_toc : clk_wiz_0
    port map ( 
   -- Clock out ports