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Mlinkó Péter
fpga_project
Commits
3894370d
Commit
3894370d
authored
6 years ago
by
Peter Mlinko
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Added Cell component to game_of_life
parent
150f22bc
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game_of_life/game_of_life.cache/wt/project.wpc
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game_of_life/game_of_life.cache/wt/project.wpc
game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
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..._of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
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game_of_life/game_of_life.cache/wt/project.wpc
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3894370d
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game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
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...
@@ -59,8 +59,25 @@ port
...
@@ -59,8 +59,25 @@ port
);
);
end
component
;
end
component
;
component
cell
port
(
clk_1hz
:
in
STD_LOGIC
;
locked
:
in
STD_LOGIC
;
switch
:
in
STD_LOGIC
;
flip_val
:
inout
STD_LOGIC
;
neighbours
:
in
STD_LOGIC_VECTOR
(
1
to
8
);
output
:
out
STD_LOGIC
);
end
component
;
signal
locked
,
inner_clk
,
one_sec_clk
:
STD_LOGIC
;
signal
locked
,
inner_clk
,
one_sec_clk
:
STD_LOGIC
;
-- the cell_outputs signal holds the output of the cells
-- the 0th element holds the boundary condition
-- we have 64×48 cells
signal
cell_outputs
:
STD_LOGIC_VECTOR
(
0
to
3072
);
begin
begin
tic_toc
:
clk_wiz_0
tic_toc
:
clk_wiz_0
...
...
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