Skip to content
Snippets Groups Projects
Commit 3894370d authored by Peter Mlinko's avatar Peter Mlinko
Browse files

Added Cell component to game_of_life

parent 150f22bc
No related branches found
No related tags found
No related merge requests found
version:1 version:1
6d6f64655f636f756e7465727c4755494d6f6465:2 6d6f64655f636f756e7465727c4755494d6f6465:3
eof: eof:
...@@ -59,8 +59,25 @@ port ...@@ -59,8 +59,25 @@ port
); );
end component; end component;
component cell
port
(
clk_1hz : in STD_LOGIC;
locked : in STD_LOGIC;
switch : in STD_LOGIC;
flip_val : inout STD_LOGIC;
neighbours : in STD_LOGIC_VECTOR(1 to 8);
output : out STD_LOGIC
);
end component;
signal locked, inner_clk, one_sec_clk : STD_LOGIC; signal locked, inner_clk, one_sec_clk : STD_LOGIC;
-- the cell_outputs signal holds the output of the cells
-- the 0th element holds the boundary condition
-- we have 64×48 cells
signal cell_outputs : STD_LOGIC_VECTOR(0 to 3072);
begin begin
tic_toc : clk_wiz_0 tic_toc : clk_wiz_0
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment