added cell.vhdl

Some basic functions are implemented, might be needed more functions

game_of_life/game_of_life.srcs/sources_1/new/cell.vhd

+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 11/26/2018 01:05:37 PM
+-- Design Name: 
+-- Module Name: game_of_life - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cell is
+    Port (
+        clk_1hz : in STD_LOGIC;                  -- this signal shows when to refresh
+        locked : in STD_LOGIC;                   -- locked shows if the gol's inner clock is locked
+        switch : in STD_LOGIC;                   -- switch between user input and automatic working
+        flip_val : inout STD_LOGIC;              -- signal to switch state if user input is activated (switch=true)
+        neighbours : in STD_LOGIC_VECTOR(1 to 8);-- state of neighbours
+        output : out STD_LOGIC                   -- output of the cell
+    );
+end cell;
+
+architecture Behavioral of cell is
+
+signal state, next_state : STD_LOGIC := '0';
+signal neighbour_count : UNSIGNED(3 downto 0);
+signal flip_val_sig : STD_LOGIC;
+
+begin
+
+    life_cycle : process(clk_1hz)               -- for now we dont care about the switches, later should written          
+    begin
+        if clk_1hz'event and clk_1hz='1' and locked='1' and switch='1' then
+            if neighbour_count=3 then
+                next_state <= '1';
+            elsif neighbour_count=2 then
+                next_state <= state;
+            elsif neighbour_count<2 or neighbour_count>3 then
+                next_state <= '0';
+            end if;
+            state <= next_state;
+        elsif clk_1hz'event and clk_1hz='1' and locked='1' and switch='0' then
+            if flip_val_sig='1' then
+                next_state <= not state;
+            end if;
+            state <= next_state;
+        end if;
+        
+    end process; -- life_cycle
+    
+    count_neighbours : process (clk_1hz)         -- this process calculates active neighbours, if the clk chages to 0
+        variable temp_count : UNSIGNED(3 downto 0);
+    begin
+        if clk_1hz'event and clk_1hz='0' and locked='1' and switch='1' then
+            temp_count := (others=>'0');
+            for n in neighbours'range loop
+                 if neighbours(n) = '1' then
+                    temp_count := temp_count+1;
+                 end if;
+            end loop;
+            neighbour_count <= temp_count;
+        end if;
+    end process; -- count_neighbours
+ 
+    handle_flip_val_input : process (flip_val)
+    begin
+        if flip_val'event and flip_val='0' then
+            flip_val_sig<='1';
+            flip_val<='0';
+        end if;
+    end process;
+ 
+end Behavioral;
\ No newline at end of file

game_of_life/game_of_life.xpr

@@ -69,6 +69,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/cell.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="game_of_life"/>