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new file mode 100644
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diff --git a/game_of_life_v2/game_of_life_v2.cache/wt/synthesis.wdf b/game_of_life_v2/game_of_life_v2.cache/wt/synthesis.wdf
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diff --git a/game_of_life_v2/game_of_life_v2.cache/wt/synthesis_details.wdf b/game_of_life_v2/game_of_life_v2.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
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diff --git a/game_of_life_v2/game_of_life_v2.cache/wt/webtalk_pa.xml b/game_of_life_v2/game_of_life_v2.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..3322af28d182ee612bc0e8370655e985b3eee847
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.cache/wt/webtalk_pa.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Mon Dec 10 15:37:40 2018">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="ce4c9e5318b847e4b9c4d067fe664fc8" type="ProjectID"/>
+<property name="ProjectIteration" value="2" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="CoreView" value="4" type="JavaHandler"/>
+<property name="CustomizeCore" value="1" type="JavaHandler"/>
+<property name="NewProject" value="1" type="JavaHandler"/>
+<property name="RunBitgen" value="1" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="5" type="GuiHandlerData"/>
+<property name="BaseDialog_YES" value="1" type="GuiHandlerData"/>
+<property name="ConstraintsChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="4" type="GuiHandlerData"/>
+<property name="CreateConstraintsFilePanel_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_TYPE" value="1" type="GuiHandlerData"/>
+<property name="DefineModulesDialog_DEFINE_MODULES_AND_SPECIFY_IO_PORTS" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="11" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="4" type="GuiHandlerData"/>
+<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="NumJobsChooser_NUMBER_OF_JOBS" value="1" type="GuiHandlerData"/>
+<property name="PartChooser_BOARDS" value="2" type="GuiHandlerData"/>
+<property name="ProgressDialog_BACKGROUND" value="1" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="3" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
+<property name="SimpleOutputProductDialog_GENERATE_OUTPUT_PRODUCTS_IMMEDIATELY" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_ADD_HDL_AND_NETLIST_FILES_TO_YOUR_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_ADD_SOURCES_FROM_SUBDIRECTORIES" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_TARGET_LANGUAGE" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserTable_SRC_CHOOSER_TABLE" value="2" type="GuiHandlerData"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100755
index 0000000000000000000000000000000000000000..86c38a5053446e477d07070392d4c9bf6427ec4e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1____25.000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ locked : out std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ locked => locked,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000000000000000000000000000000000000..2baafebb2293023a6942df054a126d29b068c195
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,21 @@
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+// Date : Mon Dec 10 14:55:55 2018
+// Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+// Command : write_verilog -force -mode synth_stub
+// /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_out1, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
+ output clk_out1;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1b2166be2347db852f700920ff290d4494d29431
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,30 @@
+-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+-- Date : Mon Dec 10 14:55:55 2018
+-- Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+-- Command : write_vhdl -force -mode synth_stub
+-- /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
+begin
+end;
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..a1326b41df11cfb3040165abee1f0b587b339d9f
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,665 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: 7 Series || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..7652088ed462fa67fca5e46691e59a79d7c942c1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,527 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: PLLE2 DRP
+// Module Name: plle2_drp_func.h
+// Version: 2.00
+// Target Devices: 7 Series || PLL
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+// Updated for CR663854.
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..f1314b0b13bc76d8e918332251f4cce2d6a09451
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,668 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: UltraScale Architecture || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b0001_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+ reg [15:0] drp_reg1;
+ reg [15:0] drp_reg2;
+ reg [5:0] drp_regshared;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ drp_regshared[5:0] = { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac};
+ drp_reg2[15:0] = { 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, 4'h0, dt[5:0] };
+ drp_reg1[15:0] = { pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] };
+ mmcm_frac_count_calc[37:0] = {drp_regshared, drp_reg2, drp_reg1} ;
+
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..d12a6f7fe9816584c57e90001041953621b99c1e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,524 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..c4978df787d556117a66789327b8683d13522aa1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,855 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..9bfa6c8b63eeea52205986810d40e98fd15064b3
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/ipstatic/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,530 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..567342e985544187497dcb2845014330f0e21e73
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/README.txt
@@ -0,0 +1,83 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required
+# to simulate the design for a simulator, the directory structure
+# and the generated exported files.
+#
+################################################################################
+
+1. Simulate Design
+
+To simulate design, cd to the simulator directory and execute the script.
+
+For example:-
+
+% cd questa
+% ./top.sh
+
+The export simulation flow requires the Xilinx pre-compiled simulation library
+components for the target simulator. These components are referred using the
+'-lib_map_path' switch. If this switch is specified, then the export simulation
+will automatically set this library path in the generated script and update,
+copy the simulator setup file(s) in the exported directory.
+
+If '-lib_map_path' is not specified, then the pre-compiled simulation library
+information will not be included in the exported scripts and that may cause
+simulation errors when running this script. Alternatively, you can provide the
+library information using this switch while executing the generated script.
+
+For example:-
+
+% ./top.sh -lib_map_path /design/questa/clibs
+
+Please refer to the generated script header 'Prerequisite' section for more details.
+
+2. Directory Structure
+
+By default, if the -directory switch is not specified, export_simulation will
+create the following directory structure:-
+
+<current_working_directory>/export_sim/<simulator>
+
+For example, if the current working directory is /tmp/test, export_simulation
+will create the following directory path:-
+
+/tmp/test/export_sim/questa
+
+If -directory switch is specified, export_simulation will create a simulator
+sub-directory under the specified directory path.
+
+For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
+command will create the following directory:-
+
+/tmp/test/my_test_area/func_sim/questa
+
+By default, if -simulator is not specified, export_simulation will create a
+simulator sub-directory for each simulator and export the files for each simulator
+in this sub-directory respectively.
+
+IMPORTANT: Please note that the simulation library path must be specified manually
+in the generated script for the respective simulator. Please refer to the generated
+script header 'Prerequisite' section for more details.
+
+3. Exported script and files
+
+Export simulation will create the driver shell script, setup files and copy the
+design sources in the output directory path.
+
+By default, when the -script_name switch is not specified, export_simulation will
+create the following script name:-
+
+<simulation_top>.sh (Unix)
+When exporting the files for an IP using the -of_objects switch, export_simulation
+will create the following script name:-
+
+<ip-name>.sh (Unix)
+Export simulation will create the setup files for the target simulator specified
+with the -simulator switch.
+
+For example, if the target simulator is "ies", export_simulation will create the
+'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
+file.
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..326592ac065bb7eef76d2f84eb07efd2dcd32b5c
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
@@ -0,0 +1,150 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy library.cfg file
+copy_setup_file()
+{
+ file="library.cfg"
+ lib_map_path=""
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..84230b86d0c870bb465c337051b9789df6be79f8
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
@@ -0,0 +1,22 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xil_defaultlib
+vlib activehdl/xpm
+
+vmap xil_defaultlib activehdl/xil_defaultlib
+vmap xpm activehdl/xpm
+
+vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7208881ddc6e6d288e0af86a22f0834eb0dd3d0e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..a31d6d90366a051f95b51d8e626272ea4673737d
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_0.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..c3fb512f92a9059141140b761dd5425d7017beec
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..d660709b94ea1a3fb55eaa6edc3843ba57266db5
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/clk_wiz_0.sh
@@ -0,0 +1,177 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Cadence Incisive Enterprise Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory
+ref_lib_dir="."
+
+# Command line options
+irun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm)
+
+# Simulation root library directory
+sim_lib_dir="ies_lib"
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+ irun $irun_opts \
+ -reflib "$ref_lib_dir/unisim:unisim" \
+ -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+ -reflib "$ref_lib_dir/secureip:secureip" \
+ -reflib "$ref_lib_dir/unimacro:unimacro" \
+ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+ -top xil_defaultlib.clk_wiz_0 \
+ -f run.f \
+ -top glbl \
+ glbl.v \
+ +incdir+"$ref_dir/../../../ipstatic" \
+ +incdir+"../../../ipstatic"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ else
+ ref_lib_dir=$2
+ fi
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(ncsim.key irun.key irun.log waves.shm irun.history .simvision INCA_libs)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..deb7b75ca4b7ce2fcf8b928dc5f09d27f07c4eb4
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f
new file mode 100644
index 0000000000000000000000000000000000000000..3ef7e92c5c698c193566160783fa19e86567dea9
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/ies/run.f
@@ -0,0 +1,14 @@
+-makelib ies_lib/xil_defaultlib -sv \
+ "/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+-endlib
+-makelib ies_lib/xpm \
+ "/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+ "../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+ "../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+-endlib
+-makelib ies_lib/xil_defaultlib \
+ glbl.v
+-endlib
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f3343e06bed75d4c7ac6c269eb64b41c2b1fcf6e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
@@ -0,0 +1,168 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="modelsim_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..9a66a6007604cf437eaddee60150ac64f0389cdd
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
@@ -0,0 +1,22 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xil_defaultlib
+vlib modelsim_lib/msim/xpm
+
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+vmap xpm modelsim_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -incr -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 -incr "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7208881ddc6e6d288e0af86a22f0834eb0dd3d0e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..a44f519ffaabace3625e85fa7804c932e15767ec
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc" -t 1ps -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run -all
+
+quit -force
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1126cbd4b8eaef68daf3c386963b977c9afaa21d
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
@@ -0,0 +1,175 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ source elaborate.do 2>&1 | tee -a elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="questa_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..8e44cc2b1d5e0dc4eebefbe6963e4071f5b38ac7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xil_defaultlib
+vlib questa_lib/msim/xpm
+
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+vmap xpm questa_lib/msim/xpm
+
+vlog -work xil_defaultlib -64 -sv "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -64 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
new file mode 100644
index 0000000000000000000000000000000000000000..b2b0781f9018de75b3bff670eb79c407f7ba372a
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7208881ddc6e6d288e0af86a22f0834eb0dd3d0e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..77fdf30baa29475631bb44d6e8bca5b7e2d20b4b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
@@ -0,0 +1,16 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -t 1ps -lib xil_defaultlib clk_wiz_0_opt
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run -all
+
+quit -force
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..bfe02a2ac099275df54a637257644b2783b96865
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
@@ -0,0 +1,152 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ source compile.do 2>&1 | tee -a compile.log
+
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy library.cfg file
+copy_setup_file()
+{
+ file="library.cfg"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..c8170c1a77787307feab560e090fcfb818ee577d
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
@@ -0,0 +1,22 @@
+vlib work
+vlib riviera
+
+vlib riviera/xil_defaultlib
+vlib riviera/xpm
+
+vmap xil_defaultlib riviera/xil_defaultlib
+vmap xpm riviera/xpm
+
+vlog -work xil_defaultlib -sv2k12 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vlog -work xil_defaultlib -v2k5 "+incdir+../../../ipstatic" "+incdir+../../../ipstatic" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..7208881ddc6e6d288e0af86a22f0834eb0dd3d0e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..a31d6d90366a051f95b51d8e626272ea4673737d
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
@@ -0,0 +1,17 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim -t 1ps +access +r +m+clk_wiz_0 -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_0.udo}
+
+run -all
+
+endsim
+
+quit -force
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..35d0f5a271cba26596da98c08af2ecb40fd1be18
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
@@ -0,0 +1,231 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Command line options
+vlogan_opts="-full64"
+vhdlan_opts="-full64"
+vcs_elab_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log"
+vcs_sim_opts="-ucli -licqueue -l simulate.log"
+
+# Design libraries
+design_libs=(xil_defaultlib xpm)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ vlogan -work xil_defaultlib $vlogan_opts -sverilog +incdir+"$ref_dir/../../../ipstatic" \
+ "/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+ 2>&1 | tee -a vlogan.log
+
+ vhdlan -work xpm $vhdlan_opts \
+ "/opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd" \
+ 2>&1 | tee -a vhdlan.log
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k +incdir+"$ref_dir/../../../ipstatic" \
+ "$ref_dir/../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+ "$ref_dir/../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+ 2>&1 | tee -a vlogan.log
+
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k \
+ glbl.v \
+ 2>&1 | tee -a vlogan.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ create_lib_mappings $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ create_lib_mappings $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+ file="synopsys_sim.setup"
+ if [[ -e $file ]]; then
+ if [[ ($1 == "") ]]; then
+ return
+ else
+ rm -rf $file
+ fi
+ fi
+
+ touch $file
+
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ mapping="$lib:$sim_lib_dir/$lib"
+ echo $mapping >> $file
+ done
+
+ if [[ ($lib_map_path != "") ]]; then
+ incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+ echo $incl_ref >> $file
+ fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_0_simv.daidir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..deb7b75ca4b7ce2fcf8b928dc5f09d27f07c4eb4
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
@@ -0,0 +1,5 @@
+xpm_cdc.sv,systemverilog,xil_defaultlib,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+xpm_VCOMP.vhd,vhdl,xpm,../opt/Xilinx/Vivado/2017.4/data/ip/xpm/xpm_VCOMP.vhd,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..58afc787f57956f65f4158e5ab8d06754b95c42e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
@@ -0,0 +1,2 @@
+run
+quit
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..e086fdf8f397ae89331dfe5e456776ea815c4029
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2017.4 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Dec 10 14:55:33 CET 2018
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c4f11c6122d5acb2c456ee2617dec8a5f2556f1e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
@@ -0,0 +1,217 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2017.4 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Dec 10 14:55:33 CET 2018
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+#
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Command line options
+xvlog_opts="--relax"
+
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2017.4 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # Compile design files
+ xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ xelab --relax --debug typical --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+ file="xsim.ini"
+ lib_map_path="/opt/Xilinx/Vivado/2017.4/data/xsim"
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ ip_file="xsim_ip.ini"
+ src_file="$lib_map_path/ip/$ip_file"
+ if [[ -e $src_file ]]; then
+ cp $src_file $file
+ else
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+ fi
+
+ # Map local design libraries to xsim.ini
+ map_local_libs
+
+ fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+ updated_mappings=()
+ local_mappings=()
+
+ # Local design libraries
+ local_libs=(xil_defaultlib)
+
+ if [[ 0 == ${#local_libs[@]} ]]; then
+ return
+ fi
+
+ file="xsim.ini"
+ file_backup="xsim.ini.bak"
+
+ if [[ -e $file ]]; then
+ rm -f $file_backup
+ # Create a backup copy of the xsim.ini file
+ cp $file $file_backup
+ # Read libraries from backup file and search in local library collection
+ while read -r line
+ do
+ IN=$line
+ # Split mapping entry with '=' delimiter to fetch library name and mapping
+ read lib_name mapping <<<$(IFS="="; echo $IN)
+ # If local library found, then construct the local mapping and add to local mapping collection
+ if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ local_mappings+=("$lib_name")
+ fi
+ # Add to updated library mapping collection
+ updated_mappings+=("$line")
+ done < "$file_backup"
+ # Append local libraries not found originally from xsim.ini
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ updated_mappings+=("$line")
+ fi
+ done
+ # Write updated mappings in xsim.ini
+ rm -f $file
+ for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+ lib_name="${updated_mappings[i]}"
+ echo $lib_name >> $file
+ done
+ else
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ mapping="$lib_name=xsim.dir/$lib_name"
+ echo $mapping >> $file
+ done
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..eef7a0f0f87e4717b7640d1bdeafaaec5afd9048
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run -all
+quit
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3c359c67aa53b8699d8fe87372573e6365fca006
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
@@ -0,0 +1,3 @@
+clk_wiz_0_clk_wiz.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+clk_wiz_0.v,verilog,xil_defaultlib,../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v,incdir="$ref_dir/../../../ipstatic"incdir="../../../ipstatic"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..be6423350a1b441d65c2ad7bf71b300b20dc7026
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
new file mode 100644
index 0000000000000000000000000000000000000000..a698a25809b21b0a02399e5b3911893580d96835
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
@@ -0,0 +1,7 @@
+verilog xil_defaultlib --include "../../../ipstatic" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v" \
+"../../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v" \
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_1.xml b/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..05af4389ab862fb2fbf5aa1e380a84493eef06e6
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="clk_wiz_0_synth_1" LaunchDir="/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+</Runs>
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_2.xml b/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..87ad3d00b805b8efed05c1d2b00c8465c94c6c2f
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+</Runs>
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4563f6667a19918fb83d19b72830fba0f56f98ae
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
@@ -0,0 +1,3 @@
+set_property SRC_FILE_INFO {cfile:/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
+set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..f00e9580c01fedbb3dfd4eb6a1f863ff5373c2d8
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="mlipe" Host="" Pid="4308">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.vivado.end.rst b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.js b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..8284d2d26aee69a53b29ed4a6b820732471ff68b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.js
@@ -0,0 +1,244 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.sh b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e1a8f5d63c48368b7026e6e71e5bdee343077bac
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/ISEWrap.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..3c537ef10c3f0e6cdfae3f5c41efebf61959d170
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..21f0f34060c1376772a419cdb93e209682322592
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
@@ -0,0 +1,167 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+set_param project.vivado.isBlockSynthRun true
+set_msg_config -msgmgr_mode ooc_run
+create_project -in_memory -part xc7z020clg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/wt [current_project]
+set_property parent.project_path /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
+set_property ip_output_repo /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_ip -quiet /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+
+set cached_ip [config_ip_cache -export -no_bom -use_project_ipc -dir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]]
+
+if { $cached_ip eq {} } {
+
+synth_design -top clk_wiz_0 -part xc7z020clg484-1 -mode out_of_context
+
+#---------------------------------------------------------
+# Generate Checkpoint/Stub/Simulation Files For IP Cache
+#---------------------------------------------------------
+# disable binary constraint mode for IPCache checkpoints
+set_param constraints.enableBinaryConstraints false
+
+catch {
+ write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp
+
+ set ipCachedFiles {}
+ write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
+ lappend ipCachedFiles clk_wiz_0_stub.v
+
+ write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
+ lappend ipCachedFiles clk_wiz_0_stub.vhdl
+
+ write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.v
+
+ write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl
+
+ config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -use_project_ipc -ip [get_ips clk_wiz_0]
+}
+
+rename_ref -prefix_all clk_wiz_0_
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef clk_wiz_0.dcp
+create_report "clk_wiz_0_synth_1_synth_report_utilization_0" "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb"
+
+if { [catch {
+ file copy -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ write_verilog -force -mode synth_stub /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode synth_stub /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_verilog -force -mode funcsim /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode funcsim /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+
+} else {
+
+
+if { [catch {
+ file copy -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ file rename -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+}; # end if cached_ip
+
+if {[file isdir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0
+ }
+}
+
+if {[file isdir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.ip_user_files/ip/clk_wiz_0
+ }
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
new file mode 100644
index 0000000000000000000000000000000000000000..dae59a96c90b9dbd943f78415231d030c30f7ae7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
@@ -0,0 +1,323 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 14:54:34 2018
+# Process ID: 4346
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.jou
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
+Command: synth_design -top clk_wiz_0 -part xc7z020clg484-1 -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 4354
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1279.297 ; gain = 85.000 ; free physical = 15078 ; free virtual = 17106
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19468]
+ Parameter CAPACITANCE bound to: DONT_CARE - type: string
+ Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
+ Parameter IBUF_LOW_PWR bound to: TRUE - type: string
+ Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
+ Parameter IOSTANDARD bound to: DEFAULT - type: string
+INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19468]
+INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: float
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
+ Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
+ Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: float
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
+ Parameter IS_PSEN_INVERTED bound to: 1'b0
+ Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
+ Parameter IS_PWRDWN_INVERTED bound to: 1'b0
+ Parameter IS_RST_INVERTED bound to: 1'b0
+ Parameter REF_JITTER1 bound to: 0.010000 - type: float
+ Parameter REF_JITTER2 bound to: 0.010000 - type: float
+ Parameter SS_EN bound to: FALSE - type: string
+ Parameter SS_MODE bound to: CENTER_HIGH - type: string
+ Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
+INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
+INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (5#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1320.828 ; gain = 126.531 ; free physical = 15091 ; free virtual = 17121
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.828 ; gain = 126.531 ; free physical = 15090 ; free virtual = 17120
+---------------------------------------------------------------------------------
+INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1583.059 ; gain = 0.000 ; free physical = 14815 ; free virtual = 16850
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:55 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16913
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:55 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16913
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for inst. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14879 ; free virtual = 16915
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16914
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16914
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1619.059 ; gain = 424.762 ; free physical = 14729 ; free virtual = 16771
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1619.059 ; gain = 424.762 ; free physical = 14729 ; free virtual = 16771
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14727 ; free virtual = 16769
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 2|
+|2 |MMCME2_ADV | 1|
+|3 |IBUF | 1|
++------+-----------+------+
+
+Report Instance Areas:
++------+---------+------------------+------+
+| |Instance |Module |Cells |
++------+---------+------------------+------+
+|1 |top | | 4|
+|2 | inst |clk_wiz_0_clk_wiz | 4|
++------+---------+------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1628.074 ; gain = 171.547 ; free physical = 14785 ; free virtual = 16827
+Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.082 ; gain = 433.777 ; free physical = 14785 ; free virtual = 16827
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:01:09 . Memory (MB): peak = 1635.074 ; gain = 465.602 ; free physical = 14793 ; free virtual = 16835
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+report_utilization: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1639.074 ; gain = 0.000 ; free physical = 14792 ; free virtual = 16835
+INFO: [Common 17-206] Exiting Vivado at Mon Dec 10 14:55:56 2018...
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..baf013dca7eec96db9bec2d126b5dc01e4495b60
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a68759dc7d6e67859e7a943ab346ed85794e64c9
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
@@ -0,0 +1,170 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 14:55:55 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+| Design : clk_wiz_0
+| Device : 7z020clg484-1
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| Slice LUTs* | 0 | 0 | 53200 | 0.00 |
+| LUT as Logic | 0 | 0 | 53200 | 0.00 |
+| LUT as Memory | 0 | 0 | 17400 | 0.00 |
+| Slice Registers | 0 | 0 | 106400 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 106400 | 0.00 |
+| Register as Latch | 0 | 0 | 106400 | 0.00 |
+| F7 Muxes | 0 | 0 | 26600 | 0.00 |
+| F8 Muxes | 0 | 0 | 13300 | 0.00 |
++-------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 0 | Yes | - | Set |
+| 0 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 140 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 |
+| RAMB18 | 0 | 0 | 280 | 0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs | 0 | 0 | 220 | 0.00 |
++-----------+------+-------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB | 1 | 0 | 200 | 0.50 |
+| Bonded IPADs | 0 | 0 | 2 | 0.00 |
+| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 4 | 0.00 |
+| PHASER_REF | 0 | 0 | 4 | 0.00 |
+| OUT_FIFO | 0 | 0 | 16 | 0.00 |
+| IN_FIFO | 0 | 0 | 16 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 4 | 0.00 |
+| IBUFDS | 0 | 0 | 192 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 |
+| ILOGIC | 0 | 0 | 200 | 0.00 |
+| OLOGIC | 0 | 0 | 200 | 0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 16 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 4 | 25.00 |
+| PLLE2_ADV | 0 | 0 | 4 | 0.00 |
+| BUFMRCE | 0 | 0 | 8 | 0.00 |
+| BUFHCE | 0 | 0 | 72 | 0.00 |
+| BUFR | 0 | 0 | 16 | 0.00 |
++------------+------+-------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 2 | 0.00 |
+| STARTUPE2 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| BUFG | 2 | Clock |
+| MMCME2_ADV | 1 | Clock |
+| IBUF | 1 | IO |
++------------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..29c43dfab4d1e122ddadcf494a2ca41138b9a26a
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc
@@ -0,0 +1,32 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# IP: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
+
+# IP: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
+
+# XDC: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property DONT_TOUCH TRUE [get_cells inst -quiet] -quiet
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/gen_run.xml b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..40de9bb2694749dcee290d5dc6b7fe86c04956ef
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/gen_run.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="clk_wiz_0_synth_1" LaunchPart="xc7z020clg484-1" LaunchTime="1544450072">
+ <File Type="VDS-TIMING-PB" Name="clk_wiz_0_timing_summary_synth.pb"/>
+ <File Type="VDS-TIMINGSUMMARY" Name="clk_wiz_0_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="clk_wiz_0.dcp"/>
+ <File Type="REPORTS-TCL" Name="clk_wiz_0_reports.tcl"/>
+ <File Type="PA-TCL" Name="clk_wiz_0.tcl"/>
+ <File Type="RDS-RDS" Name="clk_wiz_0.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="clk_wiz_0_drc_synth.rpt"/>
+ <File Type="RDS-UTIL" Name="clk_wiz_0_utilization_synth.rpt"/>
+ <File Type="RDS-UTIL-PB" Name="clk_wiz_0_utilization_synth.pb"/>
+ <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/htr.txt b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6b4f1314b71214e3b1d25e32848acd5ff7031988
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/project.wdf b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..48c609404bffb456227dbedc13542f5084b58ea1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3365323635656537656334333435613361386236663062376632653131373135:506172656e742050412070726f6a656374204944:00
+eof:210537709
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/rundef.js b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..09561526529d4400ea3a9ee99820ddd2f4fa5983
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;";
+} else {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.bat b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..220ba68254d1e93caa5e5a354253f5c9158a2334
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.log b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..e877a7fe98b2b3f3afcaf89c7f31a0368c96359a
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.log
@@ -0,0 +1,322 @@
+
+*** Running vivado
+ with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+
+
+****** Vivado v2017.4 (64-bit)
+ **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+ **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+ ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+source clk_wiz_0.tcl -notrace
+Command: synth_design -top clk_wiz_0 -part xc7z020clg484-1 -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 4354
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1279.297 ; gain = 85.000 ; free physical = 15078 ; free virtual = 17106
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0_clk_wiz' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-638] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19468]
+ Parameter CAPACITANCE bound to: DONT_CARE - type: string
+ Parameter IBUF_DELAY_VALUE bound to: 0 - type: string
+ Parameter IBUF_LOW_PWR bound to: TRUE - type: string
+ Parameter IFD_DELAY_VALUE bound to: AUTO - type: string
+ Parameter IOSTANDARD bound to: DEFAULT - type: string
+INFO: [Synth 8-256] done synthesizing module 'IBUF' (1#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19468]
+INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: float
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float
+ Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float
+ Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: float
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer
+ Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float
+ Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float
+ Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter IS_CLKINSEL_INVERTED bound to: 1'b0
+ Parameter IS_PSEN_INVERTED bound to: 1'b0
+ Parameter IS_PSINCDEC_INVERTED bound to: 1'b0
+ Parameter IS_PWRDWN_INVERTED bound to: 1'b0
+ Parameter IS_RST_INVERTED bound to: 1'b0
+ Parameter REF_JITTER1 bound to: 0.010000 - type: float
+ Parameter REF_JITTER2 bound to: 0.010000 - type: float
+ Parameter SS_EN bound to: FALSE - type: string
+ Parameter SS_MODE bound to: CENTER_HIGH - type: string
+ Parameter SS_MOD_PERIOD bound to: 10000 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (2#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:25757]
+INFO: [Synth 8-638] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
+INFO: [Synth 8-256] done synthesizing module 'BUFG' (3#1) [/opt/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:607]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0_clk_wiz' (4#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-256] done synthesizing module 'clk_wiz_0' (5#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v:70]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1320.828 ; gain = 126.531 ; free physical = 15091 ; free virtual = 17121
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.828 ; gain = 126.531 ; free physical = 15090 ; free virtual = 17120
+---------------------------------------------------------------------------------
+INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1583.059 ; gain = 0.000 ; free physical = 14815 ; free virtual = 16850
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:55 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16913
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:55 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16913
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property DONT_TOUCH = true for inst. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14879 ; free virtual = 16915
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16914
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:56 . Memory (MB): peak = 1583.059 ; gain = 388.762 ; free physical = 14878 ; free virtual = 16914
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1619.059 ; gain = 424.762 ; free physical = 14729 ; free virtual = 16771
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1619.059 ; gain = 424.762 ; free physical = 14729 ; free virtual = 16771
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:01:07 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14727 ; free virtual = 16769
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 2|
+|2 |MMCME2_ADV | 1|
+|3 |IBUF | 1|
++------+-----------+------+
+
+Report Instance Areas:
++------+---------+------------------+------+
+| |Instance |Module |Cells |
++------+---------+------------------+------+
+|1 |top | | 4|
+|2 | inst |clk_wiz_0_clk_wiz | 4|
++------+---------+------------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.074 ; gain = 433.777 ; free physical = 14729 ; free virtual = 16770
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:23 ; elapsed = 00:00:31 . Memory (MB): peak = 1628.074 ; gain = 171.547 ; free physical = 14785 ; free virtual = 16827
+Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:01:08 . Memory (MB): peak = 1628.082 ; gain = 433.777 ; free physical = 14785 ; free virtual = 16827
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:35 ; elapsed = 00:01:09 . Memory (MB): peak = 1635.074 ; gain = 465.602 ; free physical = 14793 ; free virtual = 16835
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+report_utilization: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1639.074 ; gain = 0.000 ; free physical = 14792 ; free virtual = 16835
+INFO: [Common 17-206] Exiting Vivado at Mon Dec 10 14:55:56 2018...
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.sh b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..29bd58a08d6afca41d190568efae4dd9547261d2
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/runme.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin
+else
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64
+else
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.jou b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..d2f35ee8452e707f23a1209cedddbc19e7d4cedc
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 14:54:34 2018
+# Process ID: 4346
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.jou
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
diff --git a/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.pb b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3961889c71e46d64d063c009a8f9bdec8a6ff294
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/clk_wiz_0_synth_1/vivado.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.Vivado_Implementation.queue.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/.lpr b/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/.lpr
new file mode 100644
index 0000000000000000000000000000000000000000..93ac6ba00fe6b7d248b91d832e730652b4dcfbcc
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/.lpr
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2017.4 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0"/>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/wt/project.wpc b/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/wt/project.wpc
new file mode 100644
index 0000000000000000000000000000000000000000..834da226cf3908e30536d5ca3070213c82a2f18b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.Xil/Vivado-6105-VLSI-01/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c42617463684d6f6465:1
+eof:
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.init_design.begin.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3621a9a33230ee730c560ed6425fcccff1914d93
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mlipe" Host="" Pid="6105">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.init_design.end.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.opt_design.begin.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3621a9a33230ee730c560ed6425fcccff1914d93
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mlipe" Host="" Pid="6105">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.opt_design.end.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.place_design.begin.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3621a9a33230ee730c560ed6425fcccff1914d93
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mlipe" Host="" Pid="6105">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.place_design.end.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.route_design.begin.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3621a9a33230ee730c560ed6425fcccff1914d93
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="mlipe" Host="" Pid="6105">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/.vivado.begin.rst b/game_of_life_v2/game_of_life_v2.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..7d16eaf54f711446fc69bf2548b1e5714f50433b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="mlipe" Host="" Pid="6067">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.js b/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..8284d2d26aee69a53b29ed4a6b820732471ff68b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.js
@@ -0,0 +1,244 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.sh b/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e1a8f5d63c48368b7026e6e71e5bdee343077bac
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.tcl b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..27c93096a060054293a27f0dfdba7f2cb6ea17fd
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.tcl
@@ -0,0 +1,170 @@
+#
+# Report generation script generated by Vivado
+#
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ create_project -in_memory -part xc7z020clg484-1
+ set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+ set_property webtalk.parent_dir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/wt [current_project]
+ set_property parent.project_path /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.xpr [current_project]
+ set_property ip_output_repo /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+ add_files -quiet /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp
+ read_ip -quiet /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+ read_xdc /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc
+ link_design -top game_of_life -part xc7z020clg484-1
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+ opt_design
+ write_checkpoint -force game_of_life_opt.dcp
+ create_report "impl_1_opt_report_drc_0" "report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx"
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+ implement_debug_core
+ place_design
+ write_checkpoint -force game_of_life_placed.dcp
+ create_report "impl_1_place_report_io_0" "report_io -file game_of_life_io_placed.rpt"
+ create_report "impl_1_place_report_utilization_0" "report_utilization -file game_of_life_utilization_placed.rpt -pb game_of_life_utilization_placed.pb"
+ create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file game_of_life_control_sets_placed.rpt"
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+ route_design
+ write_checkpoint -force game_of_life_routed.dcp
+ create_report "impl_1_route_report_drc_0" "report_drc -file game_of_life_drc_routed.rpt -pb game_of_life_drc_routed.pb -rpx game_of_life_drc_routed.rpx"
+ create_report "impl_1_route_report_methodology_0" "report_methodology -file game_of_life_methodology_drc_routed.rpt -pb game_of_life_methodology_drc_routed.pb -rpx game_of_life_methodology_drc_routed.rpx"
+ create_report "impl_1_route_report_power_0" "report_power -file game_of_life_power_routed.rpt -pb game_of_life_power_summary_routed.pb -rpx game_of_life_power_routed.rpx"
+ create_report "impl_1_route_report_route_status_0" "report_route_status -file game_of_life_route_status.rpt -pb game_of_life_route_status.pb"
+ create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file game_of_life_timing_summary_routed.rpt -rpx game_of_life_timing_summary_routed.rpx -warn_on_violation "
+ create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file game_of_life_incremental_reuse_routed.rpt"
+ create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file game_of_life_clock_utilization_routed.rpt"
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+ write_checkpoint -force game_of_life_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+ catch { write_mem_info -force game_of_life.mmi }
+ write_bitstream -force game_of_life.bit
+ catch {write_debug_probes -quiet -force game_of_life}
+ catch {file copy -force game_of_life.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.vdi b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..c629c3fcb62e093cc99ff80fcacdc894f9ea8c55
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.vdi
@@ -0,0 +1,280 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 15:39:54 2018
+# Process ID: 6105
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1
+# Command line: vivado -log game_of_life.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.vdi
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.jou
+#-----------------------------------------------------------
+source game_of_life.tcl -notrace
+Command: link_design -top game_of_life -part xc7z020clg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Project 1-454] Reading design checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_gen_25MHz'
+INFO: [Netlist 29-17] Analyzing 444 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'game_of_life' is not ideal for floorplanning, since the cellview 'game_of_life' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-479] Netlist was created with Vivado 2017.4
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_gen_25MHz/inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_gen_25MHz/inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_gen_25MHz/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+INFO: [Timing 38-2] Deriving generated clocks [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:29 . Memory (MB): peak = 2011.344 ; gain = 504.508 ; free physical = 14096 ; free virtual = 16278
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_gen_25MHz/inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+10 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:01:16 . Memory (MB): peak = 2011.344 ; gain = 840.918 ; free physical = 14102 ; free virtual = 16281
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2043.359 ; gain = 32.016 ; free physical = 14092 ; free virtual = 16271
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 241d76bc6
+
+Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14094 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 1e074dfad
+
+Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14094 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16273
+INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
+
+Phase 5 Shift Register Optimization
+Phase 5 Shift Register Optimization | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+Ending Logic Optimization Task | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1aba7ba33
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Common 17-83] Releasing license: Implementation
+25 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14091 ; free virtual = 16271
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx
+Command: report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Chipscope 16-241] No debug cores found in the current design.
+Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
+or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16259
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1773ec779
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16259
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16260
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ff3c4a16
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.97 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14071 ; free virtual = 16255
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+Phase 1 Placer Initialization | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+
+Phase 2 Global Placement
+Phase 2 Global Placement | Checksum: 13303f7c0
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14050 ; free virtual = 16235
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 13303f7c0
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14050 ; free virtual = 16235
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c6b634a3
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1859dd166
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1a50e74b3
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 15d432a1f
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+Phase 3 Detail Placement | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 11c3a9c75
+
+Phase 4.1.1.1 BUFG Insertion
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
+Phase 4.1.1.1 BUFG Insertion | Checksum: 11c3a9c75
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+INFO: [Place 30-746] Post Placement Timing Summary WNS=30.656. For the most accurate timing information please run report_timing.
+Phase 4.1.1 Post Placement Optimization | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+Phase 4.1 Post Commit Optimization | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+
+Phase 4.3 Placer Reporting
+Phase 4.3 Placer Reporting | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+
+Phase 4.4 Final Placement Cleanup
+Phase 4.4 Final Placement Cleanup | Checksum: 17a7b6dfb
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17a7b6dfb
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+Ending Placer Task | Checksum: 13dfdf743
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14047 ; free virtual = 16233
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14047 ; free virtual = 16233
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14042 ; free virtual = 16234
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file game_of_life_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14032 ; free virtual = 16220
+INFO: [runtcl-4] Executing : report_utilization -file game_of_life_utilization_placed.rpt -pb game_of_life_utilization_placed.pb
+report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14044 ; free virtual = 16231
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file game_of_life_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14043 ; free virtual = 16231
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+Checksum: PlaceDB: 491c0134 ConstDB: 0 ShapeSum: f4e1f60f RouteDB: 0
+
+Phase 1 Build RT Design
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_control_sets_placed.rpt b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..5421d25e9c38733cb860fb5e73b54a313e6775e0
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_control_sets_placed.rpt
@@ -0,0 +1,67 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 15:41:36 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_control_sets -verbose -file game_of_life_control_sets_placed.rpt
+| Design : game_of_life
+| Device : xc7z020
+-----------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Flip-Flop Distribution
+3. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Number of unique control sets | 5 |
+| Unused register locations in slices containing registers | 24 |
++----------------------------------------------------------+-------+
+
+
+2. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 1042 | 625 |
+| No | No | Yes | 20 | 13 |
+| No | Yes | No | 0 | 0 |
+| Yes | No | No | 2 | 1 |
+| Yes | No | Yes | 48 | 14 |
+| Yes | Yes | No | 0 | 0 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+3. Detailed Control Set Information
+-----------------------------------
+
++------------------------------+-----------------------------+-------------------------------+------------------+----------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
++------------------------------+-----------------------------+-------------------------------+------------------+----------------+
+| clk_gen_25MHz/inst/clk_out1 | shift_register_top0 | | 2 | 4 |
+| clk_gen_25MHz/inst/clk_out1 | vertical_counter[9]_i_1_n_0 | horizontal_counter[9]_i_2_n_0 | 5 | 10 |
+| clk_gen_25MHz/inst/clk_out1 | | horizontal_counter[9]_i_2_n_0 | 13 | 20 |
+| clk_gen_25MHz/inst/clk_out1 | shift_register_top0 | horizontal_counter[9]_i_2_n_0 | 9 | 38 |
+| clk_gen_25MHz/inst/clk_out1 | | | 625 | 1042 |
++------------------------------+-----------------------------+-------------------------------+------------------+----------------+
+
+
++--------+-----------------------+
+| Fanout | Number of ControlSets |
++--------+-----------------------+
+| 4 | 1 |
+| 10 | 1 |
+| 16+ | 3 |
++--------+-----------------------+
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpt b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d684341cf2e2a2491cf5be54e609b2eb600b3800
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpt
@@ -0,0 +1,41 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 15:41:26 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx
+| Design : game_of_life
+| Device : xc7z020clg484-1
+| Speed File : -1
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++--------+----------+--------------------+------------+
+| Rule | Severity | Description | Violations |
++--------+----------+--------------------+------------+
+| ZPS7-1 | Warning | PS7 block required | 1 |
++--------+----------+--------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+ZPS7-1#1 Warning
+PS7 block required
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpx b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..d61db7e771147321644b0ed672613fca195ad2c8
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpx differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_io_placed.rpt b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a07d21cc16cf0a465442ebbf951e25fd38259c73
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_io_placed.rpt
@@ -0,0 +1,526 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 15:41:36 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_io -file game_of_life_io_placed.rpt
+| Design : game_of_life
+| Device : xc7z020
+| Speed File : -1
+| Package : clg484
+| Package Version : FINAL 2012-06-26
+| Package Pin Delay Version : VERS. 2.0 2012-06-26
+-------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 16 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | | PS_MIO1_500 | PSS IO | | | | | | | | | | | | | | | |
+| A2 | | | PS_MIO2_500 | PSS IO | | | | | | | | | | | | | | | |
+| A3 | | | PS_MIO5_500 | PSS IO | | | | | | | | | | | | | | | |
+| A4 | | | PS_MIO6_500 | PSS IO | | | | | | | | | | | | | | | |
+| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A6 | | | PS_MIO13_500 | PSS IO | | | | | | | | | | | | | | | |
+| A7 | | | PS_MIO18_501 | PSS IO | | | | | | | | | | | | | | | |
+| A8 | | | PS_MIO20_501 | PSS IO | | | | | | | | | | | | | | | |
+| A9 | | | PS_MIO36_501 | PSS IO | | | | | | | | | | | | | | | |
+| A10 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| A11 | | | PS_MIO30_501 | PSS IO | | | | | | | | | | | | | | | |
+| A12 | | | PS_MIO28_501 | PSS IO | | | | | | | | | | | | | | | |
+| A13 | | | PS_MIO26_501 | PSS IO | | | | | | | | | | | | | | | |
+| A14 | | | PS_MIO22_501 | PSS IO | | | | | | | | | | | | | | | |
+| A15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A16 | | High Range | IO_L9P_T1_DQS_AD3P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A17 | | High Range | IO_L9N_T1_DQS_AD3N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A18 | | High Range | IO_L10P_T1_AD11P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A19 | | High Range | IO_L10N_T1_AD11N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A20 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| A21 | | High Range | IO_L15P_T2_DQS_AD12P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A22 | | High Range | IO_L15N_T2_DQS_AD12N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| AA1 | | | PS_DDR_DQ26_502 | PSS IO | | | | | | | | | | | | | | | |
+| AA2 | | | PS_DDR_DM3_502 | PSS IO | | | | | | | | | | | | | | | |
+| AA3 | | | PS_DDR_DQ24_502 | PSS IO | | | | | | | | | | | | | | | |
+| AA4 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA6 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA7 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA8 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA9 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA10 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| AA11 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA12 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AA13 | | High Range | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AA14 | | High Range | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AA15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AA16 | | High Range | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AA17 | | High Range | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AA18 | | High Range | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AA19 | Hsync | High Range | IO_L11N_T1_SRCC_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AA20 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| AA21 | frame[7] | High Range | IO_L8P_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AA22 | frame[5] | High Range | IO_L7P_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AB1 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB2 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB3 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| AB4 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB5 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB6 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB7 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB9 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB10 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB11 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB12 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| AB13 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| AB14 | | High Range | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AB15 | | High Range | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AB16 | | High Range | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AB17 | | High Range | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| AB18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| AB19 | frame[3] | High Range | IO_L10P_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AB20 | frame[2] | High Range | IO_L10N_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AB21 | frame[6] | High Range | IO_L8N_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| AB22 | frame[4] | High Range | IO_L7N_T1_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B1 | | | PS_DDR_DM0_502 | PSS IO | | | | | | | | | | | | | | | |
+| B2 | | | PS_DDR_DQ2_502 | PSS IO | | | | | | | | | | | | | | | |
+| B3 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
+| B4 | | | PS_MIO11_500 | PSS IO | | | | | | | | | | | | | | | |
+| B5 | | | PS_POR_B_500 | PSS IO | | | | | | | | | | | | | | | |
+| B6 | | | PS_MIO14_500 | PSS IO | | | | | | | | | | | | | | | |
+| B7 | | | PS_MIO24_501 | PSS IO | | | | | | | | | | | | | | | |
+| B8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B9 | | | PS_MIO45_501 | PSS IO | | | | | | | | | | | | | | | |
+| B10 | | | PS_MIO47_501 | PSS IO | | | | | | | | | | | | | | | |
+| B11 | | | PS_MIO43_501 | PSS IO | | | | | | | | | | | | | | | |
+| B12 | | | PS_MIO34_501 | PSS IO | | | | | | | | | | | | | | | |
+| B13 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| B14 | | | PS_MIO37_501 | PSS IO | | | | | | | | | | | | | | | |
+| B15 | | High Range | IO_L7N_T1_AD2N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B16 | | High Range | IO_L8P_T1_AD10P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L8N_T1_AD10N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B19 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B20 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B21 | | High Range | IO_L18P_T2_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B22 | | High Range | IO_L18N_T2_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C2 | | | PS_DDR_DQS_P0_502 | PSS IO | | | | | | | | | | | | | | | |
+| C3 | | | PS_DDR_DQ1_502 | PSS IO | | | | | | | | | | | | | | | |
+| C4 | | | PS_MIO9_500 | PSS IO | | | | | | | | | | | | | | | |
+| C5 | | | PS_MIO12_500 | PSS IO | | | | | | | | | | | | | | | |
+| C6 | | | VCCO_MIO0_500 | VCCO | | | | | | | any** | | | | | | | | |
+| C7 | | | PS_MIO32_501 | PSS IO | | | | | | | | | | | | | | | |
+| C8 | | | PS_MIO41_501 | PSS IO | | | | | | | | | | | | | | | |
+| C9 | | | PS_SRST_B_501 | PSS IO | | | | | | | | | | | | | | | |
+| C10 | | | PS_MIO51_501 | PSS IO | | | | | | | | | | | | | | | |
+| C11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C12 | | | PS_MIO53_501 | PSS IO | | | | | | | | | | | | | | | |
+| C13 | | | PS_MIO39_501 | PSS IO | | | | | | | | | | | | | | | |
+| C14 | | | PS_MIO49_501 | PSS IO | | | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L7P_T1_AD2P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C16 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| C17 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C18 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C19 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C20 | | High Range | IO_L14N_T2_AD4N_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C22 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D1 | | | PS_DDR_DQ0_502 | PSS IO | | | | | | | | | | | | | | | |
+| D2 | | | PS_DDR_DQS_N0_502 | PSS IO | | | | | | | | | | | | | | | |
+| D3 | | | PS_DDR_DQ3_502 | PSS IO | | | | | | | | | | | | | | | |
+| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D5 | | | PS_MIO7_500 | PSS IO | | | | | | | | | | | | | | | |
+| D6 | | | PS_MIO16_501 | PSS IO | | | | | | | | | | | | | | | |
+| D7 | | | PS_MIO27_501 | PSS IO | | | | | | | | | | | | | | | |
+| D8 | | | PS_MIO42_501 | PSS IO | | | | | | | | | | | | | | | |
+| D9 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| D10 | | | PS_MIO52_501 | PSS IO | | | | | | | | | | | | | | | |
+| D11 | | | PS_MIO48_501 | PSS IO | | | | | | | | | | | | | | | |
+| D12 | | | PS_MIO46_501 | PSS IO | | | | | | | | | | | | | | | |
+| D13 | | | PS_MIO50_501 | PSS IO | | | | | | | | | | | | | | | |
+| D14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D15 | | High Range | IO_L3N_T0_DQS_AD1N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D16 | | High Range | IO_L2P_T0_AD8P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D17 | | High Range | IO_L2N_T0_AD8N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D18 | | High Range | IO_L12P_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D19 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| D20 | | High Range | IO_L14P_T2_AD4P_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D21 | | High Range | IO_L17N_T2_AD5N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D22 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E1 | | | PS_DDR_DQ5_502 | PSS IO | | | | | | | | | | | | | | | |
+| E2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| E3 | | | PS_DDR_DQ4_502 | PSS IO | | | | | | | | | | | | | | | |
+| E4 | | | PS_MIO4_500 | PSS IO | | | | | | | | | | | | | | | |
+| E5 | | | PS_MIO8_500 | PSS IO | | | | | | | | | | | | | | | |
+| E6 | | | PS_MIO15_500 | PSS IO | | | | | | | | | | | | | | | |
+| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E8 | | | PS_MIO29_501 | PSS IO | | | | | | | | | | | | | | | |
+| E9 | | | PS_MIO17_501 | PSS IO | | | | | | | | | | | | | | | |
+| E10 | | | PS_MIO19_501 | PSS IO | | | | | | | | | | | | | | | |
+| E11 | | | PS_MIO23_501 | PSS IO | | | | | | | | | | | | | | | |
+| E12 | | | VCCO_MIO1_501 | VCCO | | | | | | | any** | | | | | | | | |
+| E13 | | | PS_MIO44_501 | PSS IO | | | | | | | | | | | | | | | |
+| E14 | | | PS_MIO40_501 | PSS IO | | | | | | | | | | | | | | | |
+| E15 | | High Range | IO_L3P_T0_DQS_AD1P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E16 | | High Range | IO_L1N_T0_AD0N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E18 | | High Range | IO_L5N_T0_AD9N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E19 | | High Range | IO_L21P_T3_DQS_AD14P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E20 | | High Range | IO_L21N_T3_DQS_AD14N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E21 | | High Range | IO_L17P_T2_AD5P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E22 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| F1 | | | PS_DDR_DQ7_502 | PSS IO | | | | | | | | | | | | | | | |
+| F2 | | | PS_DDR_DQ6_502 | PSS IO | | | | | | | | | | | | | | | |
+| F3 | | | PS_DDR_DRST_B_502 | PSS IO | | | | | | | | | | | | | | | |
+| F4 | | | PS_DDR_A13_502 | PSS IO | | | | | | | | | | | | | | | |
+| F5 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| F6 | | | PS_MIO3_500 | PSS IO | | | | | | | | | | | | | | | |
+| F7 | | | PS_CLK_500 | PSS Clock | | | | | | | | | | | | | | | |
+| F8 | | | PS_MIO_VREF_501 | PSS IO | | | | | | | | | | | | | | | |
+| F9 | | | PS_MIO31_501 | PSS IO | | | | | | | | | | | | | | | |
+| F10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F11 | | | PS_MIO21_501 | PSS IO | | | | | | | | | | | | | | | |
+| F12 | | | PS_MIO25_501 | PSS IO | | | | | | | | | | | | | | | |
+| F13 | | | PS_MIO38_501 | PSS IO | | | | | | | | | | | | | | | |
+| F14 | | | PS_MIO35_501 | PSS IO | | | | | | | | | | | | | | | |
+| F15 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| F16 | | High Range | IO_L1P_T0_AD0P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F17 | | High Range | IO_L6N_T0_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F18 | | High Range | IO_L5P_T0_AD9P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F19 | | High Range | IO_L20N_T3_AD6N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F21 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F22 | switch_mode | High Range | IO_L23N_T3_35 | INPUT | LVCMOS18 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| G1 | | | PS_DDR_DQ9_502 | PSS IO | | | | | | | | | | | | | | | |
+| G2 | | | PS_DDR_DQ8_502 | PSS IO | | | | | | | | | | | | | | | |
+| G3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G4 | | | PS_DDR_A14_502 | PSS IO | | | | | | | | | | | | | | | |
+| G5 | | | PS_DDR_A11_502 | PSS IO | | | | | | | | | | | | | | | |
+| G6 | | | PS_MIO0_500 | PSS IO | | | | | | | | | | | | | | | |
+| G7 | | | PS_MIO10_500 | PSS IO | | | | | | | | | | | | | | | |
+| G8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| G9 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| G10 | | | RSVDGND | GND | | | | | | | | | | | | | | | |
+| G11 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| G12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| G13 | | | PS_MIO33_501 | PSS IO | | | | | | | | | | | | | | | |
+| G14 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| G15 | | High Range | IO_L4P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G16 | | High Range | IO_L4N_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G18 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| G19 | | High Range | IO_L20P_T3_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G20 | | High Range | IO_L22P_T3_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G21 | | High Range | IO_L22N_T3_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G22 | | High Range | IO_L24N_T3_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| H2 | | | PS_DDR_DQS_P1_502 | PSS IO | | | | | | | | | | | | | | | |
+| H3 | | | PS_DDR_DM1_502 | PSS IO | | | | | | | | | | | | | | | |
+| H4 | | | PS_DDR_A12_502 | PSS IO | | | | | | | | | | | | | | | |
+| H5 | | | PS_DDR_A9_502 | PSS IO | | | | | | | | | | | | | | | |
+| H6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H7 | | | PS_DDR_VREF0_502 | PSS IO | | | | | | | | | | | | | | | |
+| H8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H9 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| H10 | | | VCCPLL | PSS VCCPLL | | | | | | | | | | | | | | | |
+| H11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| H12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H13 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| H14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H15 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| H16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H17 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H18 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H19 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H20 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H21 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 1.80 | | | | | | | | |
+| H22 | | High Range | IO_L24P_T3_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J1 | | | PS_DDR_DQ14_502 | PSS IO | | | | | | | | | | | | | | | |
+| J2 | | | PS_DDR_DQS_N1_502 | PSS IO | | | | | | | | | | | | | | | |
+| J3 | | | PS_DDR_A10_502 | PSS IO | | | | | | | | | | | | | | | |
+| J4 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| J5 | | | PS_DDR_A8_502 | PSS IO | | | | | | | | | | | | | | | |
+| J6 | | | PS_DDR_A7_502 | PSS IO | | | | | | | | | | | | | | | |
+| J7 | | | PS_DDR_A6_502 | PSS IO | | | | | | | | | | | | | | | |
+| J8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| J9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| J11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J16 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J17 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J18 | | High Range | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J20 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J21 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| J22 | | High Range | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K1 | | | PS_DDR_DQ13_502 | PSS IO | | | | | | | | | | | | | | | |
+| K2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K3 | | | PS_DDR_DQ15_502 | PSS IO | | | | | | | | | | | | | | | |
+| K4 | | | PS_DDR_A2_502 | PSS IO | | | | | | | | | | | | | | | |
+| K5 | | | PS_DDR_A5_502 | PSS IO | | | | | | | | | | | | | | | |
+| K6 | | | PS_DDR_A4_502 | PSS IO | | | | | | | | | | | | | | | |
+| K7 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| K8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| K10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K11 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K12 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K15 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K16 | | High Range | IO_L3P_T0_DQS_PUDC_B_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K17 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| K18 | | High Range | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K19 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K20 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K21 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L1 | | | PS_DDR_DQ10_502 | PSS IO | | | | | | | | | | | | | | | |
+| L2 | | | PS_DDR_DQ11_502 | PSS IO | | | | | | | | | | | | | | | |
+| L3 | | | PS_DDR_DQ12_502 | PSS IO | | | | | | | | | | | | | | | |
+| L4 | | | PS_DDR_A3_502 | PSS IO | | | | | | | | | | | | | | | |
+| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L6 | | | PS_DDR_BA1_502 | PSS IO | | | | | | | | | | | | | | | |
+| L7 | | | PS_DDR_BA0_502 | PSS IO | | | | | | | | | | | | | | | |
+| L8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| L9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| L11 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L12 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| L13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L16 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L17 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L18 | | High Range | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L19 | | High Range | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L20 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| L21 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L22 | | High Range | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M1 | | | PS_DDR_DQ16_502 | PSS IO | | | | | | | | | | | | | | | |
+| M2 | | | PS_DDR_DQ22_502 | PSS IO | | | | | | | | | | | | | | | |
+| M3 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| M4 | | | PS_DDR_A0_502 | PSS IO | | | | | | | | | | | | | | | |
+| M5 | | | PS_DDR_A1_502 | PSS IO | | | | | | | | | | | | | | | |
+| M6 | | | PS_DDR_BA2_502 | PSS IO | | | | | | | | | | | | | | | |
+| M7 | | | PS_DDR_VRN_502 | PSS IO | | | | | | | | | | | | | | | |
+| M8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| M10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M11 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M12 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| M13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M15 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M16 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M17 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M19 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M20 | | High Range | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M21 | | High Range | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M22 | | High Range | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N2 | | | PS_DDR_DQS_P2_502 | PSS IO | | | | | | | | | | | | | | | |
+| N3 | | | PS_DDR_DQ18_502 | PSS IO | | | | | | | | | | | | | | | |
+| N4 | | | PS_DDR_CKP_502 | PSS IO | | | | | | | | | | | | | | | |
+| N5 | | | PS_DDR_CKN_502 | PSS IO | | | | | | | | | | | | | | | |
+| N6 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| N7 | | | PS_DDR_VRP_502 | PSS IO | | | | | | | | | | | | | | | |
+| N8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| N9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| N11 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N12 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| N13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N15 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N16 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| N17 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N18 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N19 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N20 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N22 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P1 | | | PS_DDR_DM2_502 | PSS IO | | | | | | | | | | | | | | | |
+| P2 | | | PS_DDR_DQS_N2_502 | PSS IO | | | | | | | | | | | | | | | |
+| P3 | | | PS_DDR_CAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
+| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P5 | | | PS_DDR_ODT_502 | PSS IO | | | | | | | | | | | | | | | |
+| P6 | | | PS_DDR_CS_B_502 | PSS IO | | | | | | | | | | | | | | | |
+| P7 | | | PS_DDR_VREF1_502 | PSS IO | | | | | | | | | | | | | | | |
+| P8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| P10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| P12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| P14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P15 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P16 | | High Range | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P17 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P18 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P19 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| P20 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P21 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P22 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R1 | | | PS_DDR_DQ23_502 | PSS IO | | | | | | | | | | | | | | | |
+| R2 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| R3 | | | PS_DDR_DQ20_502 | PSS IO | | | | | | | | | | | | | | | |
+| R4 | | | PS_DDR_WE_B_502 | PSS IO | | | | | | | | | | | | | | | |
+| R5 | | | PS_DDR_RAS_B_502 | PSS IO | | | | | | | | | | | | | | | |
+| R6 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| R7 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| R8 | | | VCCPINT | PSS VCCINT | | | | | | | | | | | | | | | |
+| R9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| R11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R12 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| R13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| R15 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R16 | | High Range | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R18 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R19 | | High Range | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R20 | | High Range | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R21 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R22 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| T1 | | | PS_DDR_DQ19_502 | PSS IO | | | | | | | | | | | | | | | |
+| T2 | | | PS_DDR_DQ21_502 | PSS IO | | | | | | | | | | | | | | | |
+| T3 | | | PS_DDR_DQ17_502 | PSS IO | | | | | | | | | | | | | | | |
+| T4 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T5 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| T6 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| T7 | | | RSVDVCC1 | Reserved | | | | | | | | | | | | | | | |
+| T8 | | | RSVDVCC2 | Reserved | | | | | | | | | | | | | | | |
+| T9 | | | VCCPAUX | PSS VCCAUX | | | | | | | | | | | | | | | |
+| T10 | | | RSVDVCC3 | Reserved | | | | | | | | | | | | | | | |
+| T11 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| T12 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| T13 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| T14 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| T15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | any** | | | | | | | | |
+| T16 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T17 | | High Range | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T18 | | High Range | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T19 | | High Range | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T21 | | High Range | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| T22 | | High Range | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U1 | | | PS_DDR_DQ25_502 | PSS IO | | | | | | | | | | | | | | | |
+| U2 | | | PS_DDR_DQ27_502 | PSS IO | | | | | | | | | | | | | | | |
+| U3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U4 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U5 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U6 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U7 | | High Range | IO_25_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U8 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| U9 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U10 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U11 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U12 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| U13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U14 | | High Range | IO_25_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U15 | | High Range | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U16 | | High Range | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U17 | | High Range | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U18 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| U19 | | High Range | IO_0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U20 | frame[9] | High Range | IO_L5P_T0_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U21 | | High Range | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| U22 | | High Range | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| V1 | | | VCCO_DDR_502 | VCCO | | | | | | | any** | | | | | | | | |
+| V2 | | | PS_DDR_DQS_P3_502 | PSS IO | | | | | | | | | | | | | | | |
+| V3 | | | PS_DDR_CKE_502 | PSS IO | | | | | | | | | | | | | | | |
+| V4 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V5 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V7 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V8 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V9 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V10 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V11 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| V12 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| V13 | | High Range | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| V14 | | High Range | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| V15 | | High Range | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
+| V16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V17 | | High Range | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
+| V18 | frame[11] | High Range | IO_L6P_T0_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V19 | frame[10] | High Range | IO_L6N_T0_VREF_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V20 | frame[8] | High Range | IO_L5N_T0_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V21 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| V22 | | High Range | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W1 | | | PS_DDR_DQ28_502 | PSS IO | | | | | | | | | | | | | | | |
+| W2 | | | PS_DDR_DQS_N3_502 | PSS IO | | | | | | | | | | | | | | | |
+| W3 | | | PS_DDR_DQ30_502 | PSS IO | | | | | | | | | | | | | | | |
+| W4 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| W5 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W6 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W7 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W8 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W10 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W11 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W12 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
+| W13 | | High Range | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W14 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| W15 | | High Range | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W16 | | High Range | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W17 | | High Range | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W18 | | High Range | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| W20 | | High Range | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W21 | | High Range | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
+| W22 | | High Range | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y1 | | | PS_DDR_DQ31_502 | PSS IO | | | | | | | | | | | | | | | |
+| Y2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y3 | | | PS_DDR_DQ29_502 | PSS IO | | | | | | | | | | | | | | | |
+| Y4 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y5 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y6 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y7 | | High Range | VCCO_13 | VCCO | | 13 | | | | | 3.30 | | | | | | | | |
+| Y8 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y9 | clk | High Range | IO_L12P_T1_MRCC_13 | INPUT | LVCMOS33 | 13 | | | | NONE | | FIXED | | | | NONE | | | |
+| Y10 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y11 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
+| Y12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| Y13 | | High Range | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y14 | | High Range | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y15 | | High Range | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y16 | | High Range | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y17 | | High Range | VCCO_33 | VCCO | | 33 | | | | | 3.30 | | | | | | | | |
+| Y18 | | High Range | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
+| Y19 | Vsync | High Range | IO_L11P_T1_SRCC_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y20 | frame[1] | High Range | IO_L9P_T1_DQS_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y21 | frame[0] | High Range | IO_L9N_T1_DQS_33 | OUTPUT | LVCMOS33 | 33 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| Y22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
++------------+-------------+------------+-------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_opt.dcp b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..b757505f31814fe2c106b871f6f8478b8c55eed4
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diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_placed.dcp b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..b05ef6ee22bd41fa0f2b20df9ab4079d8e8b3d7a
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diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_utilization_placed.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..1c78c9cbf33477e2bf281efd64734cc29914a6d2
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diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_utilization_placed.rpt b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a619613ad7d9cb3b28400b80274b531a0f4b32f1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_utilization_placed.rpt
@@ -0,0 +1,218 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 15:41:36 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_utilization -file game_of_life_utilization_placed.rpt -pb game_of_life_utilization_placed.pb
+| Design : game_of_life
+| Device : 7z020clg484-1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------------------+------+-------+-----------+-------+
+| Slice LUTs | 3079 | 0 | 53200 | 5.79 |
+| LUT as Logic | 3077 | 0 | 53200 | 5.78 |
+| LUT as Memory | 2 | 0 | 17400 | 0.01 |
+| LUT as Distributed RAM | 0 | 0 | | |
+| LUT as Shift Register | 2 | 0 | | |
+| Slice Registers | 1112 | 0 | 106400 | 1.05 |
+| Register as Flip Flop | 1112 | 0 | 106400 | 1.05 |
+| Register as Latch | 0 | 0 | 106400 | 0.00 |
+| F7 Muxes | 305 | 0 | 26600 | 1.15 |
+| F8 Muxes | 132 | 0 | 13300 | 0.99 |
++----------------------------+------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 66 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 1044 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++-------------------------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------------------------------------+------+-------+-----------+-------+
+| Slice | 905 | 0 | 13300 | 6.80 |
+| SLICEL | 557 | 0 | | |
+| SLICEM | 348 | 0 | | |
+| LUT as Logic | 3077 | 0 | 53200 | 5.78 |
+| using O5 output only | 0 | | | |
+| using O6 output only | 3053 | | | |
+| using O5 and O6 | 24 | | | |
+| LUT as Memory | 2 | 0 | 17400 | 0.01 |
+| LUT as Distributed RAM | 0 | 0 | | |
+| LUT as Shift Register | 2 | 0 | | |
+| using O5 output only | 0 | | | |
+| using O6 output only | 2 | | | |
+| using O5 and O6 | 0 | | | |
+| LUT Flip Flop Pairs | 1061 | 0 | 53200 | 1.99 |
+| fully used LUT-FF pairs | 4 | | | |
+| LUT-FF pairs with one unused LUT output | 1055 | | | |
+| LUT-FF pairs with one unused Flip Flop | 1056 | | | |
+| Unique Control Sets | 5 | | | |
++-------------------------------------------+------+-------+-----------+-------+
+* Note: Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 140 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 |
+| RAMB18 | 0 | 0 | 280 | 0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs | 0 | 0 | 220 | 0.00 |
++-----------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB | 15 | 15 | 200 | 7.50 |
+| IOB Master Pads | 8 | | | |
+| IOB Slave Pads | 7 | | | |
+| Bonded IPADs | 0 | 0 | 2 | 0.00 |
+| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 4 | 0.00 |
+| PHASER_REF | 0 | 0 | 4 | 0.00 |
+| OUT_FIFO | 0 | 0 | 16 | 0.00 |
+| IN_FIFO | 0 | 0 | 16 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 4 | 0.00 |
+| IBUFDS | 0 | 0 | 192 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 |
+| ILOGIC | 0 | 0 | 200 | 0.00 |
+| OLOGIC | 0 | 0 | 200 | 0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 16 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 4 | 25.00 |
+| PLLE2_ADV | 0 | 0 | 4 | 0.00 |
+| BUFMRCE | 0 | 0 | 8 | 0.00 |
+| BUFHCE | 0 | 0 | 72 | 0.00 |
+| BUFR | 0 | 0 | 16 | 0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 2 | 0.00 |
+| STARTUPE2 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| LUT6 | 2475 | LUT |
+| FDRE | 1044 | Flop & Latch |
+| LUT3 | 530 | LUT |
+| MUXF7 | 305 | MuxFx |
+| MUXF8 | 132 | MuxFx |
+| FDCE | 66 | Flop & Latch |
+| LUT5 | 62 | LUT |
+| LUT4 | 17 | LUT |
+| OBUF | 14 | IO |
+| LUT2 | 14 | LUT |
+| CARRY4 | 5 | CarryLogic |
+| LUT1 | 3 | LUT |
+| SRLC32E | 2 | Distributed Memory |
+| FDPE | 2 | Flop & Latch |
+| BUFG | 2 | Clock |
+| MMCME2_ADV | 1 | Clock |
+| IBUF | 1 | IO |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/gen_run.xml b/game_of_life_v2/game_of_life_v2.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..3c9a018a3a14a50adce85159d46e4c2958ab431a
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/gen_run.xml
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7z020clg484-1" LaunchTime="1544452647">
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-DRC" Name="game_of_life.drc"/>
+ <File Type="BG-BGN" Name="game_of_life.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="game_of_life.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="game_of_life.ltx"/>
+ <File Type="BITSTR-MMI" Name="game_of_life.mmi"/>
+ <File Type="BITSTR-BMM" Name="game_of_life_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="game_of_life.nky"/>
+ <File Type="BITSTR-RBT" Name="game_of_life.rbt"/>
+ <File Type="BITSTR-MSK" Name="game_of_life.msk"/>
+ <File Type="BG-BIN" Name="game_of_life.bin"/>
+ <File Type="BG-BIT" Name="game_of_life.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="game_of_life_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="game_of_life_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="game_of_life_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="game_of_life_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="game_of_life_postroute_physopt.dcp"/>
+ <File Type="ROUTE-CLK" Name="game_of_life_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-SIMILARITY" Name="game_of_life_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-TIMING-RPX" Name="game_of_life_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-TIMING-PB" Name="game_of_life_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="game_of_life_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="game_of_life_route_status.pb"/>
+ <File Type="ROUTE-STATUS" Name="game_of_life_route_status.rpt"/>
+ <File Type="ROUTE-PWR-RPX" Name="game_of_life_power_routed.rpx"/>
+ <File Type="PLACE-IO" Name="game_of_life_io_placed.rpt"/>
+ <File Type="RDI-RDI" Name="game_of_life.vdi"/>
+ <File Type="PWROPT-TIMING" Name="game_of_life_timing_summary_pwropted.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="game_of_life_utilization_placed.pb"/>
+ <File Type="PHYSOPT-TIMING" Name="game_of_life_timing_summary_physopted.rpt"/>
+ <File Type="PWROPT-DRC" Name="game_of_life_drc_pwropted.rpt"/>
+ <File Type="PLACE-UTIL" Name="game_of_life_utilization_placed.rpt"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="game_of_life_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="OPT-TIMING" Name="game_of_life_timing_summary_opted.rpt"/>
+ <File Type="OPT-HWDEF" Name="game_of_life.hwdef"/>
+ <File Type="PWROPT-DCP" Name="game_of_life_pwropt.dcp"/>
+ <File Type="REPORTS-TCL" Name="game_of_life_reports.tcl"/>
+ <File Type="OPT-DCP" Name="game_of_life_opt.dcp"/>
+ <File Type="PLACE-DCP" Name="game_of_life_placed.dcp"/>
+ <File Type="PA-TCL" Name="game_of_life.tcl"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="game_of_life_methodology_drc_opted.rpt"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="game_of_life_incremental_reuse_pre_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="game_of_life_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-TIMING" Name="game_of_life_timing_summary_placed.rpt"/>
+ <File Type="INIT-TIMING" Name="game_of_life_timing_summary_init.rpt"/>
+ <File Type="OPT-DRC" Name="game_of_life_drc_opted.rpt"/>
+ <File Type="PLACE-CTRL" Name="game_of_life_control_sets_placed.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="game_of_life_incremental_reuse_placed.rpt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="game_of_life_postplace_pwropt.dcp"/>
+ <File Type="PHYSOPT-DCP" Name="game_of_life_physopt.dcp"/>
+ <File Type="PHYSOPT-DRC" Name="game_of_life_drc_physopted.rpt"/>
+ <File Type="ROUTE-ERROR-DCP" Name="game_of_life_routed_error.dcp"/>
+ <File Type="ROUTE-DCP" Name="game_of_life_routed.dcp"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="game_of_life_routed_bb.dcp"/>
+ <File Type="ROUTE-DRC" Name="game_of_life_drc_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="game_of_life_methodology_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-PB" Name="game_of_life_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="game_of_life_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-DRC-RPX" Name="game_of_life_drc_routed.rpx"/>
+ <File Type="ROUTE-PWR" Name="game_of_life_power_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="game_of_life_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-PWR-SUM" Name="game_of_life_power_summary_routed.pb"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="game_of_life"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/new/constraints.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
+ <Desc>Default settings for Implementation.</Desc>
+ </StratHandle>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/htr.txt b/game_of_life_v2/game_of_life_v2.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..4f78ef8dfc9d01bb1516194902c67e3e837713b0
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log game_of_life.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/init_design.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/init_design.pb
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diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/opt_design.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/opt_design.pb
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index 0000000000000000000000000000000000000000..4c6c06e992af2a126d167ebbe8591f28c6141259
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diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/place_design.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/place_design.pb
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index 0000000000000000000000000000000000000000..4a1576f5a63b4af57edf091e526cb35e1cbb2986
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/impl_1/place_design.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/project.wdf b/game_of_life_v2/game_of_life_v2.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..9382c33dd6835c969a6a68fcfddc6d49f006fb42
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
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+eof:1412559954
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/route_design.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..73199a5e22bc3908d52fcc709c8b269a3147ccb1
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/impl_1/route_design.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/rundef.js b/game_of_life_v2/game_of_life_v2.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..1235ac925240ffe9824d4ad29504e5996f726c13
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/rundef.js
@@ -0,0 +1,44 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;";
+} else {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log game_of_life.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.bat b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..220ba68254d1e93caa5e5a354253f5c9158a2334
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.log b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..71cd8f6b5ab23579fdf4ad39599be7d0cdadc9c7
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.log
@@ -0,0 +1,279 @@
+
+*** Running vivado
+ with args -log game_of_life.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace
+
+
+****** Vivado v2017.4 (64-bit)
+ **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+ **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+ ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+source game_of_life.tcl -notrace
+Command: link_design -top game_of_life -part xc7z020clg484-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Project 1-454] Reading design checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'clk_gen_25MHz'
+INFO: [Netlist 29-17] Analyzing 444 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'game_of_life' is not ideal for floorplanning, since the cellview 'game_of_life' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-479] Netlist was created with Vivado 2017.4
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_gen_25MHz/inst'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'clk_gen_25MHz/inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_gen_25MHz/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+INFO: [Timing 38-2] Deriving generated clocks [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:29 . Memory (MB): peak = 2011.344 ; gain = 504.508 ; free physical = 14096 ; free virtual = 16278
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'clk_gen_25MHz/inst'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+10 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:21 ; elapsed = 00:01:16 . Memory (MB): peak = 2011.344 ; gain = 840.918 ; free physical = 14102 ; free virtual = 16281
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2043.359 ; gain = 32.016 ; free physical = 14092 ; free virtual = 16271
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 241d76bc6
+
+Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.20 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14094 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 1e074dfad
+
+Time (s): cpu = 00:00:00.32 ; elapsed = 00:00:00.28 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14094 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.36 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16273
+INFO: [Opt 31-389] Phase Sweep created 11 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:00.48 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells
+
+Phase 5 Shift Register Optimization
+Phase 5 Shift Register Optimization | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+Ending Logic Optimization Task | Checksum: 2064984a9
+
+Time (s): cpu = 00:00:00.58 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1aba7ba33
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14093 ; free virtual = 16272
+INFO: [Common 17-83] Releasing license: Implementation
+25 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14091 ; free virtual = 16271
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx
+Command: report_drc -file game_of_life_drc_opted.rpt -pb game_of_life_drc_opted.pb -rpx game_of_life_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Coretcl 2-168] The results of DRC are in file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Chipscope 16-241] No debug cores found in the current design.
+Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
+or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16259
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 1773ec779
+
+Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16259
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14079 ; free virtual = 16260
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: ff3c4a16
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.97 . Memory (MB): peak = 2055.359 ; gain = 0.000 ; free physical = 14071 ; free virtual = 16255
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+Phase 1 Placer Initialization | Checksum: 16c753abf
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2058.371 ; gain = 3.012 ; free physical = 14061 ; free virtual = 16246
+
+Phase 2 Global Placement
+Phase 2 Global Placement | Checksum: 13303f7c0
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14050 ; free virtual = 16235
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 13303f7c0
+
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14050 ; free virtual = 16235
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1c6b634a3
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1859dd166
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 1a50e74b3
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14049 ; free virtual = 16234
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 15d432a1f
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+Phase 3 Detail Placement | Checksum: 16834cfa1
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14045 ; free virtual = 16231
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 11c3a9c75
+
+Phase 4.1.1.1 BUFG Insertion
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
+INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
+Phase 4.1.1.1 BUFG Insertion | Checksum: 11c3a9c75
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+INFO: [Place 30-746] Post Placement Timing Summary WNS=30.656. For the most accurate timing information please run report_timing.
+Phase 4.1.1 Post Placement Optimization | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+Phase 4.1 Post Commit Optimization | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14036 ; free virtual = 16222
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+
+Phase 4.3 Placer Reporting
+Phase 4.3 Placer Reporting | Checksum: 11740db6a
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+
+Phase 4.4 Final Placement Cleanup
+Phase 4.4 Final Placement Cleanup | Checksum: 17a7b6dfb
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 17a7b6dfb
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14037 ; free virtual = 16223
+Ending Placer Task | Checksum: 13dfdf743
+
+Time (s): cpu = 00:00:10 ; elapsed = 00:00:07 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14047 ; free virtual = 16233
+INFO: [Common 17-83] Releasing license: Implementation
+47 Infos, 2 Warnings, 1 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2082.383 ; gain = 27.023 ; free physical = 14047 ; free virtual = 16233
+Writing placer database...
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14042 ; free virtual = 16234
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file game_of_life_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14032 ; free virtual = 16220
+INFO: [runtcl-4] Executing : report_utilization -file game_of_life_utilization_placed.rpt -pb game_of_life_utilization_placed.pb
+report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14044 ; free virtual = 16231
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file game_of_life_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2082.383 ; gain = 0.000 ; free physical = 14043 ; free virtual = 16231
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 4 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs
+Checksum: PlaceDB: 491c0134 ConstDB: 0 ShapeSum: f4e1f60f RouteDB: 0
+
+Phase 1 Build RT Design
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.sh b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..32e8767f5240cfd4cdef1505bf00c3ab05bc1e8b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin
+else
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64
+else
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log game_of_life.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.jou b/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..4733a66f25bf970017bace3fa2e83d77fa8dc3e1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 15:39:54 2018
+# Process ID: 6105
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1
+# Command line: vivado -log game_of_life.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source game_of_life.tcl -notrace
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/game_of_life.vdi
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.jou
+#-----------------------------------------------------------
+source game_of_life.tcl -notrace
diff --git a/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.pb b/game_of_life_v2/game_of_life_v2.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/.Vivado_Synthesis.queue.rst b/game_of_life_v2/game_of_life_v2.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/game_of_life_propImpl.xdc b/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/game_of_life_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4a171de4dd83ae01c80ee4571196bd41255fcce1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/game_of_life_propImpl.xdc
@@ -0,0 +1,41 @@
+set_property SRC_FILE_INFO {cfile:/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc rfile:../../../game_of_life_v2.srcs/constrs_1/new/constraints.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN Y9 [get_ports {clk}]; # "GCLK"
+set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN Y21 [get_ports {frame[0]}]; # "VGA-B1"
+set_property src_info {type:XDC file:1 line:4 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN Y20 [get_ports {frame[1]}]; # "VGA-B2"
+set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AB20 [get_ports {frame[2]}]; # "VGA-B3"
+set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AB19 [get_ports {frame[3]}]; # "VGA-B4"
+set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AB22 [get_ports {frame[4]}]; # "VGA-G1"
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AA22 [get_ports {frame[5]}]; # "VGA-G2"
+set_property src_info {type:XDC file:1 line:9 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AB21 [get_ports {frame[6]}]; # "VGA-G3"
+set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AA21 [get_ports {frame[7]}]; # "VGA-G4"
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN AA19 [get_ports {Hsync}]; # "VGA-HS"
+set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V20 [get_ports {frame[8]}]; # "VGA-R1"
+set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U20 [get_ports {frame[9]}]; # "VGA-R2"
+set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V19 [get_ports {frame[10]}]; # "VGA-R3"
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V18 [get_ports {frame[11]}]; # "VGA-R4"
+set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN Y19 [get_ports {Vsync}]; # "VGA-VS"
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN F22 [get_ports {switch_mode}]; # "SW0"
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]];
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]];
+set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design]
+set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]];
+set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
+set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]];
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/.vivado.begin.rst b/game_of_life_v2/game_of_life_v2.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..678b75a62ee4f81baa9b2cbcef7a77f739ac48f3
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="mlipe" Host="" Pid="5882">
+ </Process>
+</ProcessHandle>
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/.vivado.end.rst b/game_of_life_v2/game_of_life_v2.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.js b/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..8284d2d26aee69a53b29ed4a6b820732471ff68b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.js
@@ -0,0 +1,244 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.sh b/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..e1a8f5d63c48368b7026e6e71e5bdee343077bac
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,63 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+ISE_USER=$USER
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..707a86ab54638149088e7e912a4860d054b5ca76
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.tcl b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..9c21d51809dae445aa94391b4aef2368633ec4b9
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.tcl
@@ -0,0 +1,57 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+create_project -in_memory -part xc7z020clg484-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/wt [current_project]
+set_property parent.project_path /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property board_part em.avnet.com:zed:part0:1.3 [current_project]
+set_property ip_output_repo /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+read_vhdl -library xil_defaultlib /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd
+read_ip -quiet /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc
+set_property used_in_implementation false [get_files /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+
+
+synth_design -top game_of_life -part xc7z020clg484-1
+
+
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef game_of_life.dcp
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file game_of_life_utilization_synth.rpt -pb game_of_life_utilization_synth.pb"
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.vds b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.vds
new file mode 100644
index 0000000000000000000000000000000000000000..2d49c52c288dcd70d593fe65e709de7139ddde0d
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.vds
@@ -0,0 +1,442 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 15:37:28 2018
+# Process ID: 5920
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1
+# Command line: vivado -log game_of_life.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.vds
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.jou
+#-----------------------------------------------------------
+source game_of_life.tcl -notrace
+Command: synth_design -top game_of_life -part xc7z020clg484-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 5929
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1279.293 ; gain = 84.992 ; free physical = 14677 ; free virtual = 16836
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'game_of_life' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:47]
+ Parameter cell_number bound to: 32 - type: integer
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/realtime/clk_wiz_0_stub.vhdl:5' bound to instance 'clk_gen_25MHz' of component 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:88]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/realtime/clk_wiz_0_stub.vhdl:14]
+WARNING: [Synth 8-6014] Unused sequential element neighbour_cnt_reg was removed. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:147]
+INFO: [Synth 8-256] done synthesizing module 'game_of_life' (1#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:47]
+WARNING: [Synth 8-3331] design game_of_life has unconnected port switch_mode
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1328.824 ; gain = 134.523 ; free physical = 14681 ; free virtual = 16840
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.824 ; gain = 134.523 ; free physical = 14683 ; free virtual = 16842
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc] for cell 'clk_gen_25MHz'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc] for cell 'clk_gen_25MHz'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 33]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:26]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 35]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:28]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 13]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:29]
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/game_of_life_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/game_of_life_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1697.891 ; gain = 0.000 ; free physical = 14374 ; free virtual = 16550
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14471 ; free virtual = 16642
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14471 ; free virtual = 16641
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for clk. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc, line 3).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for clk. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc, line 4).
+Applied set_property DONT_TOUCH = true for clk_gen_25MHz. (constraint file auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14473 ; free virtual = 16643
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "vertical_counter" won't be mapped to RAM because it is too sparse
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:56 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14464 ; free virtual = 16634
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 10 Bit Adders := 2
+ 2 Input 7 Bit Adders := 1
+ 9 Input 4 Bit Adders := 1
++---Registers :
+ 1024 Bit Registers := 2
+ 32 Bit Registers := 2
+ 12 Bit Registers := 2
+ 10 Bit Registers := 2
+ 9 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 1024 Bit Muxes := 5
+ 2 Input 32 Bit Muxes := 1
+ 2 Input 12 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 6
+ 4 Input 1 Bit Muxes := 2
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report
+Module game_of_life
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 10 Bit Adders := 2
+ 2 Input 7 Bit Adders := 1
+ 9 Input 4 Bit Adders := 1
++---Registers :
+ 1024 Bit Registers := 2
+ 32 Bit Registers := 2
+ 12 Bit Registers := 2
+ 10 Bit Registers := 2
+ 9 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 1024 Bit Muxes := 5
+ 2 Input 32 Bit Muxes := 1
+ 2 Input 12 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 6
+ 4 Input 1 Bit Muxes := 2
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5546] ROM "p_0_out" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "vertical_counter" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design game_of_life has unconnected port switch_mode
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[31]' (FDCE) to 'neighbours_reg[7]'
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[30]' (FDCE) to 'neighbours_reg[4]'
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[29]' (FDCE) to 'neighbours_reg[1]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[768]' (FDE) to 'cells_to_draw_reg[768]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[769]' (FDE) to 'cells_to_draw_reg[769]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[770]' (FDE) to 'cells_to_draw_reg[770]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[771]' (FDE) to 'cells_to_draw_reg[771]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[772]' (FDE) to 'cells_to_draw_reg[772]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[773]' (FDE) to 'cells_to_draw_reg[773]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[774]' (FDE) to 'cells_to_draw_reg[774]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[775]' (FDE) to 'cells_to_draw_reg[775]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[776]' (FDE) to 'cells_to_draw_reg[776]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[777]' (FDE) to 'cells_to_draw_reg[777]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[778]' (FDE) to 'cells_to_draw_reg[778]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[779]' (FDE) to 'cells_to_draw_reg[779]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[780]' (FDE) to 'cells_to_draw_reg[780]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[781]' (FDE) to 'cells_to_draw_reg[781]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[782]' (FDE) to 'cells_to_draw_reg[782]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[783]' (FDE) to 'cells_to_draw_reg[783]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[784]' (FDE) to 'cells_to_draw_reg[784]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[785]' (FDE) to 'cells_to_draw_reg[785]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[786]' (FDE) to 'cells_to_draw_reg[786]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[787]' (FDE) to 'cells_to_draw_reg[787]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[788]' (FDE) to 'cells_to_draw_reg[788]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[789]' (FDE) to 'cells_to_draw_reg[789]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[790]' (FDE) to 'cells_to_draw_reg[790]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[791]' (FDE) to 'cells_to_draw_reg[791]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[792]' (FDE) to 'cells_to_draw_reg[792]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[793]' (FDE) to 'cells_to_draw_reg[793]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[794]' (FDE) to 'cells_to_draw_reg[794]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[795]' (FDE) to 'cells_to_draw_reg[795]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[796]' (FDE) to 'cells_to_draw_reg[796]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[797]' (FDE) to 'cells_to_draw_reg[797]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[798]' (FDE) to 'cells_to_draw_reg[798]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[799]' (FDE) to 'cells_to_draw_reg[799]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[800]' (FDE) to 'cells_to_draw_reg[800]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[801]' (FDE) to 'cells_to_draw_reg[801]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[802]' (FDE) to 'cells_to_draw_reg[802]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[803]' (FDE) to 'cells_to_draw_reg[803]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[804]' (FDE) to 'cells_to_draw_reg[804]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[805]' (FDE) to 'cells_to_draw_reg[805]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[806]' (FDE) to 'cells_to_draw_reg[806]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[807]' (FDE) to 'cells_to_draw_reg[807]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[808]' (FDE) to 'cells_to_draw_reg[808]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[809]' (FDE) to 'cells_to_draw_reg[809]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[810]' (FDE) to 'cells_to_draw_reg[810]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[811]' (FDE) to 'cells_to_draw_reg[811]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[812]' (FDE) to 'cells_to_draw_reg[812]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[813]' (FDE) to 'cells_to_draw_reg[813]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[814]' (FDE) to 'cells_to_draw_reg[814]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[815]' (FDE) to 'cells_to_draw_reg[815]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[816]' (FDE) to 'cells_to_draw_reg[816]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[817]' (FDE) to 'cells_to_draw_reg[817]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[818]' (FDE) to 'cells_to_draw_reg[818]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[819]' (FDE) to 'cells_to_draw_reg[819]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[820]' (FDE) to 'cells_to_draw_reg[820]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[821]' (FDE) to 'cells_to_draw_reg[821]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[822]' (FDE) to 'cells_to_draw_reg[822]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[823]' (FDE) to 'cells_to_draw_reg[823]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[824]' (FDE) to 'cells_to_draw_reg[824]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[825]' (FDE) to 'cells_to_draw_reg[825]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[826]' (FDE) to 'cells_to_draw_reg[826]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[827]' (FDE) to 'cells_to_draw_reg[827]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[828]' (FDE) to 'cells_to_draw_reg[828]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[829]' (FDE) to 'cells_to_draw_reg[829]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[830]' (FDE) to 'cells_to_draw_reg[830]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[831]' (FDE) to 'cells_to_draw_reg[831]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[832]' (FDE) to 'cells_to_draw_reg[832]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[833]' (FDE) to 'cells_to_draw_reg[833]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[834]' (FDE) to 'cells_to_draw_reg[834]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[835]' (FDE) to 'cells_to_draw_reg[835]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[836]' (FDE) to 'cells_to_draw_reg[836]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[837]' (FDE) to 'cells_to_draw_reg[837]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[838]' (FDE) to 'cells_to_draw_reg[838]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[839]' (FDE) to 'cells_to_draw_reg[839]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[840]' (FDE) to 'cells_to_draw_reg[840]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[841]' (FDE) to 'cells_to_draw_reg[841]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[842]' (FDE) to 'cells_to_draw_reg[842]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[843]' (FDE) to 'cells_to_draw_reg[843]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[844]' (FDE) to 'cells_to_draw_reg[844]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[845]' (FDE) to 'cells_to_draw_reg[845]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[846]' (FDE) to 'cells_to_draw_reg[846]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[847]' (FDE) to 'cells_to_draw_reg[847]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[848]' (FDE) to 'cells_to_draw_reg[848]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[849]' (FDE) to 'cells_to_draw_reg[849]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[850]' (FDE) to 'cells_to_draw_reg[850]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[851]' (FDE) to 'cells_to_draw_reg[851]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[852]' (FDE) to 'cells_to_draw_reg[852]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[853]' (FDE) to 'cells_to_draw_reg[853]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[854]' (FDE) to 'cells_to_draw_reg[854]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[855]' (FDE) to 'cells_to_draw_reg[855]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[856]' (FDE) to 'cells_to_draw_reg[856]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[857]' (FDE) to 'cells_to_draw_reg[857]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[858]' (FDE) to 'cells_to_draw_reg[858]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[859]' (FDE) to 'cells_to_draw_reg[859]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[860]' (FDE) to 'cells_to_draw_reg[860]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[861]' (FDE) to 'cells_to_draw_reg[861]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[862]' (FDE) to 'cells_to_draw_reg[862]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[863]' (FDE) to 'cells_to_draw_reg[863]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[864]' (FDE) to 'cells_to_draw_reg[864]'
+INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14418 ; free virtual = 16581
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_gen_25MHz/clk_out1' to pin 'clk_gen_25MHz/bbstub_clk_out1/O'
+INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:03 ; elapsed = 00:01:36 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14302 ; free virtual = 16466
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:01:30 ; elapsed = 00:02:03 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14234 ; free virtual = 16395
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:01:31 ; elapsed = 00:02:05 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14228 ; free virtual = 16390
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+Static Shift Register Report:
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+|game_of_life | neighbours_reg[6] | 30 | 2 | YES | NO | YES | 0 | 2 |
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+-----------------+------+
+| |Cell |Count |
++------+-----------------+------+
+|1 |clk_wiz_0_bbox_0 | 1|
+|2 |CARRY4 | 5|
+|3 |LUT1 | 4|
+|4 |LUT2 | 14|
+|5 |LUT3 | 530|
+|6 |LUT4 | 17|
+|7 |LUT5 | 62|
+|8 |LUT6 | 2475|
+|9 |MUXF7 | 305|
+|10 |MUXF8 | 132|
+|11 |SRLC32E | 2|
+|12 |FDCE | 66|
+|13 |FDPE | 2|
+|14 |FDRE | 1033|
+|15 |OBUF | 14|
++------+-----------------+------+
+
+Report Instance Areas:
++------+---------+-------+------+
+| |Instance |Module |Cells |
++------+---------+-------+------+
+|1 |top | | 4663|
++------+---------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:01:25 ; elapsed = 00:01:32 . Memory (MB): peak = 1832.242 ; gain = 268.875 ; free physical = 14287 ; free virtual = 16451
+Synthesis Optimization Complete : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.250 ; gain = 637.941 ; free physical = 14292 ; free virtual = 16456
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 442 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'game_of_life' is not ideal for floorplanning, since the cellview 'game_of_life' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+126 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:39 ; elapsed = 00:02:12 . Memory (MB): peak = 1832.250 ; gain = 662.781 ; free physical = 14354 ; free virtual = 16518
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file game_of_life_utilization_synth.rpt -pb game_of_life_utilization_synth.pb
+report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1856.254 ; gain = 0.000 ; free physical = 14356 ; free virtual = 16520
+INFO: [Common 17-206] Exiting Vivado at Mon Dec 10 15:39:53 2018...
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.pb b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..c1f57626d33090407b4158ee8571089822e57894
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.rpt b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..c79f53fe57c5d1e8cc3294a3d30478ba81ade506
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life_utilization_synth.rpt
@@ -0,0 +1,185 @@
+Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+| Date : Mon Dec 10 15:39:53 2018
+| Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+| Command : report_utilization -file game_of_life_utilization_synth.rpt -pb game_of_life_utilization_synth.pb
+| Design : game_of_life
+| Device : 7z020clg484-1
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------------------+------+-------+-----------+-------+
+| Slice LUTs* | 3079 | 0 | 53200 | 5.79 |
+| LUT as Logic | 3077 | 0 | 53200 | 5.78 |
+| LUT as Memory | 2 | 0 | 17400 | 0.01 |
+| LUT as Distributed RAM | 0 | 0 | | |
+| LUT as Shift Register | 2 | 0 | | |
+| Slice Registers | 1101 | 0 | 106400 | 1.03 |
+| Register as Flip Flop | 1101 | 0 | 106400 | 1.03 |
+| Register as Latch | 0 | 0 | 106400 | 0.00 |
+| F7 Muxes | 305 | 0 | 26600 | 1.15 |
+| F8 Muxes | 132 | 0 | 13300 | 0.99 |
++----------------------------+------+-------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 2 | Yes | - | Set |
+| 66 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 1033 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 140 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 140 | 0.00 |
+| RAMB18 | 0 | 0 | 280 | 0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs | 0 | 0 | 220 | 0.00 |
++-----------+------+-------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB | 14 | 0 | 200 | 7.00 |
+| Bonded IPADs | 0 | 0 | 2 | 0.00 |
+| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 4 | 0.00 |
+| PHASER_REF | 0 | 0 | 4 | 0.00 |
+| OUT_FIFO | 0 | 0 | 16 | 0.00 |
+| IN_FIFO | 0 | 0 | 16 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 4 | 0.00 |
+| IBUFDS | 0 | 0 | 192 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 16 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 16 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 200 | 0.00 |
+| ILOGIC | 0 | 0 | 200 | 0.00 |
+| OLOGIC | 0 | 0 | 200 | 0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL | 0 | 0 | 32 | 0.00 |
+| BUFIO | 0 | 0 | 16 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 4 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 4 | 0.00 |
+| BUFMRCE | 0 | 0 | 8 | 0.00 |
+| BUFHCE | 0 | 0 | 72 | 0.00 |
+| BUFR | 0 | 0 | 16 | 0.00 |
++------------+------+-------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 2 | 0.00 |
+| STARTUPE2 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| LUT6 | 2475 | LUT |
+| FDRE | 1033 | Flop & Latch |
+| LUT3 | 530 | LUT |
+| MUXF7 | 305 | MuxFx |
+| MUXF8 | 132 | MuxFx |
+| FDCE | 66 | Flop & Latch |
+| LUT5 | 62 | LUT |
+| LUT4 | 17 | LUT |
+| OBUF | 14 | IO |
+| LUT2 | 14 | LUT |
+| CARRY4 | 5 | CarryLogic |
+| LUT1 | 4 | LUT |
+| SRLC32E | 2 | Distributed Memory |
+| FDPE | 2 | Flop & Latch |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/gen_run.xml b/game_of_life_v2/game_of_life_v2.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..901d5a4a41908f5288f05cdcd2bd113c289bc399
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/gen_run.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7z020clg484-1" LaunchTime="1544452647">
+ <File Type="VDS-TIMING-PB" Name="game_of_life_timing_summary_synth.pb"/>
+ <File Type="VDS-TIMINGSUMMARY" Name="game_of_life_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="game_of_life.dcp"/>
+ <File Type="REPORTS-TCL" Name="game_of_life_reports.tcl"/>
+ <File Type="PA-TCL" Name="game_of_life.tcl"/>
+ <File Type="RDS-RDS" Name="game_of_life.vds"/>
+ <File Type="RDS-PROPCONSTRS" Name="game_of_life_drc_synth.rpt"/>
+ <File Type="RDS-UTIL" Name="game_of_life_utilization_synth.rpt"/>
+ <File Type="RDS-UTIL-PB" Name="game_of_life_utilization_synth.pb"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="game_of_life"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/new/constraints.xdc">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
+ <Desc>Vivado Synthesis Defaults</Desc>
+ </StratHandle>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/htr.txt b/game_of_life_v2/game_of_life_v2.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..be2818a43a5e50324de401151e9edee11cc2f531
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log game_of_life.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/rundef.js b/game_of_life_v2/game_of_life_v2.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..371cd66da1d8074e83150f982b778b3e32d705fa
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;";
+} else {
+ PathVal = "/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64;/opt/Xilinx/Vivado/2017.4/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log game_of_life.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.bat b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..220ba68254d1e93caa5e5a354253f5c9158a2334
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.log b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..376c638f2e80cc9b84797411857dc502a0ac8b64
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.log
@@ -0,0 +1,441 @@
+
+*** Running vivado
+ with args -log game_of_life.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl
+
+
+****** Vivado v2017.4 (64-bit)
+ **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+ **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+ ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+
+source game_of_life.tcl -notrace
+Command: synth_design -top game_of_life -part xc7z020clg484-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 5929
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1279.293 ; gain = 84.992 ; free physical = 14677 ; free virtual = 16836
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'game_of_life' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:47]
+ Parameter cell_number bound to: 32 - type: integer
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/realtime/clk_wiz_0_stub.vhdl:5' bound to instance 'clk_gen_25MHz' of component 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:88]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/realtime/clk_wiz_0_stub.vhdl:14]
+WARNING: [Synth 8-6014] Unused sequential element neighbour_cnt_reg was removed. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:147]
+INFO: [Synth 8-256] done synthesizing module 'game_of_life' (1#1) [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/new/game_of_life.vhd:47]
+WARNING: [Synth 8-3331] design game_of_life has unconnected port switch_mode
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1328.824 ; gain = 134.523 ; free physical = 14681 ; free virtual = 16840
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1328.824 ; gain = 134.523 ; free physical = 14683 ; free virtual = 16842
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xc7z020clg484-1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc] for cell 'clk_gen_25MHz'
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc] for cell 'clk_gen_25MHz'
+Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 33]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:26]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 34]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:27]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 35]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:28]
+WARNING: [Vivado 12-584] No ports matched '[get_ports -of_objects [get_iobanks 13]]'. [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc:29]
+Finished Parsing XDC File [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/constrs_1/new/constraints.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/game_of_life_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/game_of_life_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1697.891 ; gain = 0.000 ; free physical = 14374 ; free virtual = 16550
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14471 ; free virtual = 16642
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z020clg484-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14471 ; free virtual = 16641
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for clk. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc, line 3).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for clk. (constraint file /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/.Xil/Vivado-5920-VLSI-01/dcp1/clk_wiz_0_in_context.xdc, line 4).
+Applied set_property DONT_TOUCH = true for clk_gen_25MHz. (constraint file auto generated constraint, line ).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:54 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14473 ; free virtual = 16643
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "vertical_counter" won't be mapped to RAM because it is too sparse
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:56 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14464 ; free virtual = 16634
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 10 Bit Adders := 2
+ 2 Input 7 Bit Adders := 1
+ 9 Input 4 Bit Adders := 1
++---Registers :
+ 1024 Bit Registers := 2
+ 32 Bit Registers := 2
+ 12 Bit Registers := 2
+ 10 Bit Registers := 2
+ 9 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 1024 Bit Muxes := 5
+ 2 Input 32 Bit Muxes := 1
+ 2 Input 12 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 6
+ 4 Input 1 Bit Muxes := 2
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report
+Module game_of_life
+Detailed RTL Component Info :
++---Adders :
+ 2 Input 10 Bit Adders := 2
+ 2 Input 7 Bit Adders := 1
+ 9 Input 4 Bit Adders := 1
++---Registers :
+ 1024 Bit Registers := 2
+ 32 Bit Registers := 2
+ 12 Bit Registers := 2
+ 10 Bit Registers := 2
+ 9 Bit Registers := 1
+ 1 Bit Registers := 4
++---Muxes :
+ 2 Input 1024 Bit Muxes := 5
+ 2 Input 32 Bit Muxes := 1
+ 2 Input 12 Bit Muxes := 1
+ 2 Input 9 Bit Muxes := 1
+ 3 Input 1 Bit Muxes := 2
+ 2 Input 1 Bit Muxes := 6
+ 4 Input 1 Bit Muxes := 2
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 220 (col length:60)
+BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5546] ROM "p_0_out" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Hsync_sig" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "vertical_counter" won't be mapped to RAM because it is too sparse
+INFO: [Synth 8-5546] ROM "Vsync_sig" won't be mapped to RAM because it is too sparse
+WARNING: [Synth 8-3331] design game_of_life has unconnected port switch_mode
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[31]' (FDCE) to 'neighbours_reg[7]'
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[30]' (FDCE) to 'neighbours_reg[4]'
+INFO: [Synth 8-3886] merging instance 'shift_register_top_reg[29]' (FDCE) to 'neighbours_reg[1]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[768]' (FDE) to 'cells_to_draw_reg[768]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[769]' (FDE) to 'cells_to_draw_reg[769]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[770]' (FDE) to 'cells_to_draw_reg[770]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[771]' (FDE) to 'cells_to_draw_reg[771]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[772]' (FDE) to 'cells_to_draw_reg[772]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[773]' (FDE) to 'cells_to_draw_reg[773]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[774]' (FDE) to 'cells_to_draw_reg[774]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[775]' (FDE) to 'cells_to_draw_reg[775]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[776]' (FDE) to 'cells_to_draw_reg[776]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[777]' (FDE) to 'cells_to_draw_reg[777]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[778]' (FDE) to 'cells_to_draw_reg[778]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[779]' (FDE) to 'cells_to_draw_reg[779]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[780]' (FDE) to 'cells_to_draw_reg[780]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[781]' (FDE) to 'cells_to_draw_reg[781]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[782]' (FDE) to 'cells_to_draw_reg[782]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[783]' (FDE) to 'cells_to_draw_reg[783]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[784]' (FDE) to 'cells_to_draw_reg[784]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[785]' (FDE) to 'cells_to_draw_reg[785]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[786]' (FDE) to 'cells_to_draw_reg[786]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[787]' (FDE) to 'cells_to_draw_reg[787]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[788]' (FDE) to 'cells_to_draw_reg[788]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[789]' (FDE) to 'cells_to_draw_reg[789]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[790]' (FDE) to 'cells_to_draw_reg[790]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[791]' (FDE) to 'cells_to_draw_reg[791]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[792]' (FDE) to 'cells_to_draw_reg[792]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[793]' (FDE) to 'cells_to_draw_reg[793]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[794]' (FDE) to 'cells_to_draw_reg[794]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[795]' (FDE) to 'cells_to_draw_reg[795]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[796]' (FDE) to 'cells_to_draw_reg[796]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[797]' (FDE) to 'cells_to_draw_reg[797]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[798]' (FDE) to 'cells_to_draw_reg[798]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[799]' (FDE) to 'cells_to_draw_reg[799]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[800]' (FDE) to 'cells_to_draw_reg[800]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[801]' (FDE) to 'cells_to_draw_reg[801]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[802]' (FDE) to 'cells_to_draw_reg[802]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[803]' (FDE) to 'cells_to_draw_reg[803]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[804]' (FDE) to 'cells_to_draw_reg[804]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[805]' (FDE) to 'cells_to_draw_reg[805]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[806]' (FDE) to 'cells_to_draw_reg[806]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[807]' (FDE) to 'cells_to_draw_reg[807]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[808]' (FDE) to 'cells_to_draw_reg[808]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[809]' (FDE) to 'cells_to_draw_reg[809]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[810]' (FDE) to 'cells_to_draw_reg[810]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[811]' (FDE) to 'cells_to_draw_reg[811]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[812]' (FDE) to 'cells_to_draw_reg[812]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[813]' (FDE) to 'cells_to_draw_reg[813]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[814]' (FDE) to 'cells_to_draw_reg[814]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[815]' (FDE) to 'cells_to_draw_reg[815]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[816]' (FDE) to 'cells_to_draw_reg[816]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[817]' (FDE) to 'cells_to_draw_reg[817]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[818]' (FDE) to 'cells_to_draw_reg[818]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[819]' (FDE) to 'cells_to_draw_reg[819]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[820]' (FDE) to 'cells_to_draw_reg[820]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[821]' (FDE) to 'cells_to_draw_reg[821]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[822]' (FDE) to 'cells_to_draw_reg[822]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[823]' (FDE) to 'cells_to_draw_reg[823]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[824]' (FDE) to 'cells_to_draw_reg[824]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[825]' (FDE) to 'cells_to_draw_reg[825]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[826]' (FDE) to 'cells_to_draw_reg[826]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[827]' (FDE) to 'cells_to_draw_reg[827]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[828]' (FDE) to 'cells_to_draw_reg[828]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[829]' (FDE) to 'cells_to_draw_reg[829]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[830]' (FDE) to 'cells_to_draw_reg[830]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[831]' (FDE) to 'cells_to_draw_reg[831]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[832]' (FDE) to 'cells_to_draw_reg[832]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[833]' (FDE) to 'cells_to_draw_reg[833]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[834]' (FDE) to 'cells_to_draw_reg[834]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[835]' (FDE) to 'cells_to_draw_reg[835]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[836]' (FDE) to 'cells_to_draw_reg[836]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[837]' (FDE) to 'cells_to_draw_reg[837]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[838]' (FDE) to 'cells_to_draw_reg[838]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[839]' (FDE) to 'cells_to_draw_reg[839]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[840]' (FDE) to 'cells_to_draw_reg[840]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[841]' (FDE) to 'cells_to_draw_reg[841]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[842]' (FDE) to 'cells_to_draw_reg[842]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[843]' (FDE) to 'cells_to_draw_reg[843]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[844]' (FDE) to 'cells_to_draw_reg[844]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[845]' (FDE) to 'cells_to_draw_reg[845]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[846]' (FDE) to 'cells_to_draw_reg[846]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[847]' (FDE) to 'cells_to_draw_reg[847]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[848]' (FDE) to 'cells_to_draw_reg[848]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[849]' (FDE) to 'cells_to_draw_reg[849]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[850]' (FDE) to 'cells_to_draw_reg[850]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[851]' (FDE) to 'cells_to_draw_reg[851]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[852]' (FDE) to 'cells_to_draw_reg[852]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[853]' (FDE) to 'cells_to_draw_reg[853]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[854]' (FDE) to 'cells_to_draw_reg[854]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[855]' (FDE) to 'cells_to_draw_reg[855]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[856]' (FDE) to 'cells_to_draw_reg[856]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[857]' (FDE) to 'cells_to_draw_reg[857]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[858]' (FDE) to 'cells_to_draw_reg[858]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[859]' (FDE) to 'cells_to_draw_reg[859]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[860]' (FDE) to 'cells_to_draw_reg[860]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[861]' (FDE) to 'cells_to_draw_reg[861]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[862]' (FDE) to 'cells_to_draw_reg[862]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[863]' (FDE) to 'cells_to_draw_reg[863]'
+INFO: [Synth 8-3886] merging instance 'cells_reg[864]' (FDE) to 'cells_to_draw_reg[864]'
+INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:56 ; elapsed = 00:01:25 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14418 ; free virtual = 16581
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+INFO: [Synth 8-5578] Moved timing constraint from pin 'clk_gen_25MHz/clk_out1' to pin 'clk_gen_25MHz/bbstub_clk_out1/O'
+INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:03 ; elapsed = 00:01:36 . Memory (MB): peak = 1697.891 ; gain = 503.590 ; free physical = 14302 ; free virtual = 16466
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:01:30 ; elapsed = 00:02:03 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14234 ; free virtual = 16395
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:01:31 ; elapsed = 00:02:05 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14228 ; free virtual = 16390
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+
+Report Check Netlist:
++------+------------------+-------+---------+-------+------------------+
+| |Item |Errors |Warnings |Status |Description |
++------+------------------+-------+---------+-------+------------------+
+|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+
+Report RTL Partitions:
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:01:32 ; elapsed = 00:02:06 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14229 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+
+Static Shift Register Report:
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+|game_of_life | neighbours_reg[6] | 30 | 2 | YES | NO | YES | 0 | 2 |
++-------------+-------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP and Shift Register Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+-----------------+------+
+| |Cell |Count |
++------+-----------------+------+
+|1 |clk_wiz_0_bbox_0 | 1|
+|2 |CARRY4 | 5|
+|3 |LUT1 | 4|
+|4 |LUT2 | 14|
+|5 |LUT3 | 530|
+|6 |LUT4 | 17|
+|7 |LUT5 | 62|
+|8 |LUT6 | 2475|
+|9 |MUXF7 | 305|
+|10 |MUXF8 | 132|
+|11 |SRLC32E | 2|
+|12 |FDCE | 66|
+|13 |FDPE | 2|
+|14 |FDRE | 1033|
+|15 |OBUF | 14|
++------+-----------------+------+
+
+Report Instance Areas:
++------+---------+-------+------+
+| |Instance |Module |Cells |
++------+---------+-------+------+
+|1 |top | | 4663|
++------+---------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.242 ; gain = 637.941 ; free physical = 14227 ; free virtual = 16391
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:01:25 ; elapsed = 00:01:32 . Memory (MB): peak = 1832.242 ; gain = 268.875 ; free physical = 14287 ; free virtual = 16451
+Synthesis Optimization Complete : Time (s): cpu = 00:01:35 ; elapsed = 00:02:09 . Memory (MB): peak = 1832.250 ; gain = 637.941 ; free physical = 14292 ; free virtual = 16456
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Netlist 29-17] Analyzing 442 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+WARNING: [Netlist 29-101] Netlist 'game_of_life' is not ideal for floorplanning, since the cellview 'game_of_life' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+126 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:39 ; elapsed = 00:02:12 . Memory (MB): peak = 1832.250 ; gain = 662.781 ; free physical = 14354 ; free virtual = 16518
+INFO: [Common 17-1381] The checkpoint '/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file game_of_life_utilization_synth.rpt -pb game_of_life_utilization_synth.pb
+report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 1856.254 ; gain = 0.000 ; free physical = 14356 ; free virtual = 16520
+INFO: [Common 17-206] Exiting Vivado at Mon Dec 10 15:39:53 2018...
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.sh b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a058f9d06c4d44c9c520904f592818a192ca1813
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/runme.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin
+else
+ PATH=/opt/Xilinx/SDK/2017.4/bin:/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2017.4/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64
+else
+ LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/lin64:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log game_of_life.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.jou b/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..4a6eda960efd71d56f3f742e81a90b2dc1c20ffc
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2017.4 (64-bit)
+# SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
+# IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
+# Start of session at: Mon Dec 10 15:37:28 2018
+# Process ID: 5920
+# Current directory: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1
+# Command line: vivado -log game_of_life.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source game_of_life.tcl
+# Log file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/game_of_life.vds
+# Journal file: /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.jou
+#-----------------------------------------------------------
+source game_of_life.tcl -notrace
diff --git a/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.pb b/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..6ca4558463b2a9bf8d7ea2d5d807af3315cbfcd2
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.runs/synth_1/vivado.pb differ
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..3c537ef10c3f0e6cdfae3f5c41efebf61959d170
Binary files /dev/null and b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..e4068ca2b7aa4c5d057cdd1b9ce128bb05616e1c
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.v
@@ -0,0 +1,90 @@
+
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____25.000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_4_3_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_0
+ (
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ output locked,
+ // Clock in ports
+ input clk_in1
+ );
+
+ clk_wiz_0_clk_wiz inst
+ (
+ // Clock out ports
+ .clk_out1(clk_out1),
+ // Status and control signals
+ .locked(locked),
+ // Clock in ports
+ .clk_in1(clk_in1)
+ );
+
+endmodule
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000000000000000000000000000000000000..86c38a5053446e477d07070392d4c9bf6427ec4e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1____25.000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ locked : out std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ locked => locked,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
new file mode 100644
index 0000000000000000000000000000000000000000..bb911dd94788847c36d33bd443a07a75d6b7e6f3
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
@@ -0,0 +1,668 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>xci</spirit:library>
+ <spirit:name>unknown</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clk_wiz_0</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.4"/>
+ <spirit:configurableElementValues>
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+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.25</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.25</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.25</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">9.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1____25.000______0.000______50.0______181.828____104.359</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">181.828</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">104.359</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">25.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">sys_clock</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">9.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD">em.avnet.com:zed:part0:1.3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2017.4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ <spirit:vendorExtensions>
+ <xilinx:componentInstanceExtensions>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:componentInstanceExtensions>
+ </spirit:vendorExtensions>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..a5da024413b409b225482781dc91bd6264e7f40b
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
@@ -0,0 +1,60 @@
+
+# file: clk_wiz_0.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.000 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0a6c224ce8e653deba42d809f57585c0572e8c85
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
@@ -0,0 +1,4792 @@
+<?xml version="1.0" encoding="UTF-8"?>
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+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>clk_wiz_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
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+ </spirit:physicalPort>
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+ </spirit:physicalPort>
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+ <spirit:portMap>
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+ <spirit:physicalPort>
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+ <spirit:name>ADDR_WIDTH</spirit:name>
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+ <spirit:name>BUSER_WIDTH</spirit:name>
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+ <spirit:name>C_PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLATFORM" spirit:order="204">UNKNOWN</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREQ_SYNTH" spirit:order="205">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT" spirit:order="206">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_JITTER" spirit:order="207">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER" spirit:order="208">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_JITTER_SEL" spirit:order="209">No_Jitter</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_POWER" spirit:order="210">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MIN_O_JITTER" spirit:order="211">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_MAX_I_JITTER" spirit:order="212">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT" spirit:order="213">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER" spirit:order="214">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_DYN_RECONFIG" spirit:order="215">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM" spirit:order="216">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FAST_SIMULATION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FAST_SIMULATION" spirit:order="217">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMTYPE_SEL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMTYPE_SEL" spirit:order="218">AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLK_VALID" spirit:order="219">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_FREQ" spirit:order="220">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD" spirit:order="220.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IN_FREQ_UNITS" spirit:order="221">Units_MHz</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ" spirit:order="222">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD" spirit:order="222.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FEEDBACK_SOURCE" spirit:order="223">FDBK_AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PHASESHIFT_MODE" spirit:order="2240">WAVEFORM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_SOURCE" spirit:order="225">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING" spirit:order="226">SINGLE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_RESET</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_RESET_LOW</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_STATUS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock Freq (MHz) Input Jitter (UI)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+ <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">clk_out1____25.000______0.000______50.0______181.828____104.359</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">no_CLK_OUT2_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">no_CLK_OUT3_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">no_CLK_OUT4_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">25.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">25.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">9.125</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">36.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">reset</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_REG</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_REG" spirit:order="409">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_2" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVCLK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVCLK" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_3" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE1_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE1_AUTO" spirit:order="411">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
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+ <spirit:name>clk_wiz_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ0</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ0" spirit:order="15200">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ1</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ1" spirit:order="15200">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ2</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ2" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ3</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ3" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLOCK_MONITOR</spirit:name>
+ <spirit:displayName>Enable Clock Monitoring</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLOCK_MONITOR" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK2</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK2" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK3</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK3" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REF_CLK_FREQ</spirit:name>
+ <spirit:displayName>Reference Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:order="15300" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRECISION</spirit:name>
+ <spirit:displayName>Tolerance(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRECISION" spirit:order="15400" spirit:minimum="1" spirit:maximum="100">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMITIVE</spirit:name>
+ <spirit:displayName>Primitive</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMTYPE_SEL</spirit:name>
+ <spirit:displayName>Primtype Sel</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+ <spirit:displayName>Clock Mgr Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHASESHIFT_MODE" spirit:choiceRef="choice_list_1d3de01d" spirit:order="116" spirit:configGroups="0 NoDisplay">WAVEFORM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_JITTER_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RELATIVE_INCLK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_OPTIONS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">25.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING" spirit:order="984" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING" spirit:order="985" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING" spirit:order="986" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING" spirit:order="987" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING" spirit:order="988" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING" spirit:order="989" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING" spirit:order="990" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUMMARY_STRINGS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CALC_DONE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_RESET</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_STATUS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">reset</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="106" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">9.125</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">36.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_TYPE</spirit:name>
+ <spirit:displayName>Reset Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_BOARD_FLOW</spirit:name>
+ <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_c6542ce1" spirit:order="13.8">sys_clock</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_c6542ce1" spirit:order="13.9">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AUTO_PRIMITIVE" spirit:choiceRef="choice_pairs_77d3d587" spirit:order="13212">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CDDC</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_JITTER</spirit:name>
+ <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">181.828</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout1 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">104.359</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_JITTER</spirit:name>
+ <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout2 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_JITTER</spirit:name>
+ <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout3 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_JITTER</spirit:name>
+ <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout4 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_JITTER</spirit:name>
+ <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout5 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_JITTER</spirit:name>
+ <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout6 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_JITTER</spirit:name>
+ <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout7 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="7.8">frequency</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AXI_DRP</spirit:name>
+ <spirit:displayName>Write DRP registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_DRP" spirit:order="11.12">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+ <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+ <xilinx:xpmLibraries>
+ <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+ </xilinx:xpmLibraries>
+ <xilinx:coreRevision>3</xilinx:coreRevision>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2017.4</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="47eccc34"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0eced063"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0f2f17dd"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="488ef609"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..6c74a3a2d79bbb73e4f6e60b82e505303d762858
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
@@ -0,0 +1,3 @@
+#--------------------Physical Constraints-----------------
+
+set_property BOARD_PIN {sys_clk} [get_ports clk_in1]
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
new file mode 100644
index 0000000000000000000000000000000000000000..ba800e7dbaa823e85dd64c7b360a90a26ff5d822
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
@@ -0,0 +1,201 @@
+
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1____25.000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_0_clk_wiz
+
+ (// Clock in ports
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ output locked,
+ input clk_in1
+ );
+ // Input buffering
+ //------------------------------------
+wire clk_in1_clk_wiz_0;
+wire clk_in2_clk_wiz_0;
+ IBUF clkin1_ibufg
+ (.O (clk_in1_clk_wiz_0),
+ .I (clk_in1));
+
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4_clk_wiz_0;
+ wire clk_out5_clk_wiz_0;
+ wire clk_out6_clk_wiz_0;
+ wire clk_out7_clk_wiz_0;
+
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1_unused;
+ wire clkout1b_unused;
+ wire clkout2_unused;
+ wire clkout2b_unused;
+ wire clkout3_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (9.125),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (36.500),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.000))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_clk_wiz_0),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1_clk_wiz_0),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clkout1_unused),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clkout2_unused),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clkout3_unused),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_clk_wiz_0),
+ .CLKIN1 (clk_in1_clk_wiz_0),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (1'b0));
+
+ assign locked = locked_int;
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_clk_wiz_0),
+ .I (clkfbout_clk_wiz_0));
+
+
+
+
+
+
+ BUFG clkout1_buf
+ (.O (clk_out1),
+ .I (clk_out1_clk_wiz_0));
+
+
+
+
+endmodule
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..9305712f8063f46a6eaf6dbd3546536f2fe269d5
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
@@ -0,0 +1,58 @@
+
+# file: clk_wiz_0_ooc.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints #
+############################################################
+#create_clock -period 10.000 [get_ports clk_in1]
+
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
new file mode 100644
index 0000000000000000000000000000000000000000..36b61831b2acd26b186fa468d50c47aaaddcd5f1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,238 @@
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+// Date : Mon Dec 10 14:55:55 2018
+// Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+// Command : write_verilog -force -mode funcsim
+// /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7z020clg484-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module clk_wiz_0
+ (clk_out1,
+ locked,
+ clk_in1);
+ output clk_out1;
+ output locked;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire locked;
+
+ clk_wiz_0_clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .locked(locked));
+endmodule
+
+(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
+module clk_wiz_0_clk_wiz_0_clk_wiz
+ (clk_out1,
+ locked,
+ clk_in1);
+ output clk_out1;
+ output locked;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire locked;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(9.125000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(36.500000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(locked),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(1'b0));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..b341e6e400709bbf52dafd0727d178b640be1212
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,187 @@
+-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+-- Date : Mon Dec 10 14:55:55 2018
+-- Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+-- Command : write_vhdl -force -mode funcsim
+-- /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7z020clg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0_clk_wiz_0_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute ORIG_REF_NAME : string;
+ attribute ORIG_REF_NAME of clk_wiz_0_clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
+end clk_wiz_0_clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of clk_wiz_0_clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 9.125000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 36.500000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => locked,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => '0'
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0 is
+ port (
+ clk_out1 : out STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of clk_wiz_0 : entity is true;
+end clk_wiz_0;
+
+architecture STRUCTURE of clk_wiz_0 is
+begin
+inst: entity work.clk_wiz_0_clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ locked => locked
+ );
+end STRUCTURE;
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000000000000000000000000000000000000..2baafebb2293023a6942df054a126d29b068c195
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,21 @@
+// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+// Date : Mon Dec 10 14:55:55 2018
+// Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+// Command : write_verilog -force -mode synth_stub
+// /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7z020clg484-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_out1, locked, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,locked,clk_in1" */;
+ output clk_out1;
+ output locked;
+ input clk_in1;
+endmodule
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..1b2166be2347db852f700920ff290d4494d29431
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,30 @@
+-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
+-- Date : Mon Dec 10 14:55:55 2018
+-- Host : VLSI-01 running 64-bit Ubuntu 16.04.5 LTS
+-- Command : write_vhdl -force -mode synth_stub
+-- /home/mlipe/dev/fpga_project/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7z020clg484-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ locked : out STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
+begin
+end;
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v5_4_changelog.txt b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v5_4_changelog.txt
new file mode 100755
index 0000000000000000000000000000000000000000..c6994bde885f4d5ce9e32def95f035c799122299
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/doc/clk_wiz_v5_4_changelog.txt
@@ -0,0 +1,167 @@
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 CR-991054
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2017 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
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+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..a1326b41df11cfb3040165abee1f0b587b339d9f
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,665 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: 7 Series || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..7652088ed462fa67fca5e46691e59a79d7c942c1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,527 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: PLLE2 DRP
+// Module Name: plle2_drp_func.h
+// Version: 2.00
+// Target Devices: 7 Series || PLL
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+// Updated for CR663854.
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..f1314b0b13bc76d8e918332251f4cce2d6a09451
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,668 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: UltraScale Architecture || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b0001_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+ reg [15:0] drp_reg1;
+ reg [15:0] drp_reg2;
+ reg [5:0] drp_regshared;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ drp_regshared[5:0] = { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac};
+ drp_reg2[15:0] = { 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, 4'h0, dt[5:0] };
+ drp_reg1[15:0] = { pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0] };
+ mmcm_frac_count_calc[37:0] = {drp_regshared, drp_reg2, drp_reg1} ;
+
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..d12a6f7fe9816584c57e90001041953621b99c1e
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,524 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..c4978df787d556117a66789327b8683d13522aa1
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,855 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..9bfa6c8b63eeea52205986810d40e98fd15064b3
--- /dev/null
+++ b/game_of_life_v2/game_of_life_v2.srcs/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,530 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+