From 81d173bf155eb6d6252d416536be3b0032140aeb Mon Sep 17 00:00:00 2001
From: Peter Mlinko <link@hatchet>
Date: Tue, 27 Nov 2018 14:21:01 +0100
Subject: [PATCH] Added one_sec_clock to game_of_life
---
.../game_of_life.cache/wt/project.wpc | 2 +-
.../sources_1/new/game_of_life.vhd | 19 ++++++++++++++-
game_of_life/game_of_life.xpr | 24 +++++++------------
3 files changed, 27 insertions(+), 18 deletions(-)
diff --git a/game_of_life/game_of_life.cache/wt/project.wpc b/game_of_life/game_of_life.cache/wt/project.wpc
index 9b34209..6888ede 100644
--- a/game_of_life/game_of_life.cache/wt/project.wpc
+++ b/game_of_life/game_of_life.cache/wt/project.wpc
@@ -1,3 +1,3 @@
version:1
-6d6f64655f636f756e7465727c4755494d6f6465:1
+6d6f64655f636f756e7465727c4755494d6f6465:2
eof:
diff --git a/game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd b/game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
index 8e5b255..47b6f07 100644
--- a/game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
+++ b/game_of_life/game_of_life.srcs/sources_1/new/game_of_life.vhd
@@ -50,7 +50,16 @@ port
);
end component;
-signal locked, inner_clk : STD_LOGIC;
+component one_second_clock
+port
+ (
+ clock_in : in STD_LOGIC;
+ locked : in STD_LOGIC;
+ clock_out : out STD_LOGIC
+ );
+end component;
+
+signal locked, inner_clk, one_sec_clk : STD_LOGIC;
begin
@@ -64,6 +73,14 @@ tic_toc : clk_wiz_0
clk_in1 => clk_sys
);
+one_hertz_gen : one_second_clock
+ port map
+ (
+ clock_in => inner_clk,
+ locked => locked,
+ clock_out => one_sec_clk
+);
+
synchron : process(inner_clk)
begin
--
diff --git a/game_of_life/game_of_life.xpr b/game_of_life/game_of_life.xpr
index 4d3fef0..c140a47 100644
--- a/game_of_life/game_of_life.xpr
+++ b/game_of_life/game_of_life.xpr
@@ -3,7 +3,7 @@
<!-- -->
<!-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -->
-<Project Version="7" Minor="35" Path="/home/vagle/fpga_project/game_of_life/game_of_life.xpr">
+<Project Version="7" Minor="35" Path="/home/link/Documents/ppke/fpga/fpga_project/game_of_life/game_of_life.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="371a98f33a2a4b6a881ffa6392349aed"/>
@@ -57,15 +57,14 @@
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
- <File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
+ <File Path="$PSRCDIR/sources_1/new/one_second_clock.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
- <File Path="$PSRCDIR/sources_1/new/one_second_clock.vhd">
+ <File Path="$PSRCDIR/sources_1/new/game_of_life.vhd">
<FileInfo>
- <Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
@@ -89,6 +88,7 @@
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+ <Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="game_of_life"/>
@@ -137,9 +137,7 @@
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
@@ -147,9 +145,7 @@
</Run>
<Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7z020clg484-1" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -158,9 +154,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
- <Desc>Default settings for Implementation.</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -176,9 +170,7 @@
</Run>
<Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg484-1" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017">
- <Desc>Default settings for Implementation.</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
--
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